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Searched refs:set_wptr (Results 1 – 25 of 32) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dradeon_asic.c195 .set_wptr = &r100_gfx_set_wptr,
345 .set_wptr = &r100_gfx_set_wptr,
359 .set_wptr = &r100_gfx_set_wptr,
916 .set_wptr = &r600_gfx_set_wptr,
929 .set_wptr = &r600_dma_set_wptr,
1014 .set_wptr = &uvd_v1_0_set_wptr,
1213 .set_wptr = &uvd_v1_0_set_wptr,
1320 .set_wptr = &r600_gfx_set_wptr,
1333 .set_wptr = &r600_dma_set_wptr,
1629 .set_wptr = &cayman_gfx_set_wptr,
[all …]
H A Dradeon.h1820 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2730 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ring.h148 void (*set_wptr)(struct amdgpu_ring *ring); member
262 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
H A Dvce_v3_0.c901 .set_wptr = vce_v3_0_ring_set_wptr,
925 .set_wptr = vce_v3_0_ring_set_wptr,
H A Duvd_v6_0.c1525 .set_wptr = uvd_v6_0_ring_set_wptr,
1551 .set_wptr = uvd_v6_0_ring_set_wptr,
1580 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
H A Djpeg_v3_0.c557 .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
H A Dvce_v2_0.c612 .set_wptr = vce_v2_0_ring_set_wptr,
H A Dsdma_v4_0.c2305 .set_wptr = sdma_v4_0_ring_set_wptr,
2341 .set_wptr = sdma_v4_0_ring_set_wptr,
2373 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2405 .set_wptr = sdma_v4_0_page_ring_set_wptr,
H A Djpeg_v2_5.c572 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
H A Duvd_v3_1.c182 .set_wptr = uvd_v3_1_ring_set_wptr,
H A Duvd_v4_2.c745 .set_wptr = uvd_v4_2_ring_set_wptr,
H A Djpeg_v1_0.c550 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
H A Duvd_v5_0.c854 .set_wptr = uvd_v5_0_ring_set_wptr,
H A Djpeg_v2_0.c780 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
H A Dsi_dma.c727 .set_wptr = si_dma_ring_set_wptr,
H A Dvcn_v1_0.c1906 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1940 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
H A Duvd_v7_0.c1780 .set_wptr = uvd_v7_0_ring_set_wptr,
1813 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
H A Dvcn_v2_5.c1531 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1631 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
H A Dvcn_v2_0.c2010 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2041 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
H A Dvcn_v3_0.c1660 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1760 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
H A Dmes_v10_1.c81 .set_wptr = mes_v10_1_ring_set_wptr,
H A Dsdma_v2_4.c1142 .set_wptr = sdma_v2_4_ring_set_wptr,
H A Dvce_v4_0.c1074 .set_wptr = vce_v4_0_ring_set_wptr,
H A Dcik_sdma.c1252 .set_wptr = cik_sdma_ring_set_wptr,
H A Dsdma_v3_0.c1580 .set_wptr = sdma_v3_0_ring_set_wptr,

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