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Searched refs:rockchip_pll_get_rate (Results 1 – 20 of 20) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3308.c154 old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_armclk_set_clk()
180 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
186 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
189 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
192 priv->vpll1_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_clk_get_pll_rate()
269 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
272 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_mac_set_clk()
275 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
939 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_clk_get_rate()
943 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_rate()
[all …]
H A Dclk_rk1808.c493 parent = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_get_clk()
502 parent = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_get_clk()
603 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_mac_set_clk()
606 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[PPLL], in rk1808_mac_set_clk()
609 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_mac_set_clk()
877 old_rate = rockchip_pll_get_rate(&rk1808_pll_clks[APLL], in rk1808_armclk_set_clk()
903 return rockchip_pll_get_rate(&rk1808_pll_clks[APLL], priv->cru, APLL); in rk1808_armclk_set_clk()
919 rate = rockchip_pll_get_rate(&rk1808_pll_clks[clk->id - 1], in rk1808_clk_get_rate()
923 rate = rockchip_pll_get_rate(&rk1808_pll_clks[APLL], in rk1808_clk_get_rate()
1286 rockchip_pll_get_rate(&rk1808_pll_clks[APLL], in rk1808_clk_probe()
[all …]
H A Dclk_rk3128.c108 old_rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
490 parent = rockchip_pll_get_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_get_rate()
539 rate = rockchip_pll_get_rate(&rk3128_pll_clks[clk->id - 1], in rk3128_clk_get_rate()
543 rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_clk_get_rate()
810 if (rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rkclk_init()
814 priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
848 rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_clk_probe()
853 rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_clk_probe()
H A Dclk_rk3588.c1096 parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_get_clk()
1157 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1516 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_get_rate()
1522 rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru, in rk3588_clk_get_rate()
1526 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru, in rk3588_clk_get_rate()
1530 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru, in rk3588_clk_get_rate()
1534 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1538 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1542 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1546 rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_get_rate()
[all …]
H A Dclk_rk3328.c135 old_rate = rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rk3328_armclk_set_clk()
163 return rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], priv->cru, NPLL); in rk3328_armclk_set_clk()
788 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_get_rate()
793 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_get_rate()
805 rate = rockchip_pll_get_rate(&rk3328_pll_clks[clk->id - 1], in rk3328_clk_get_rate()
809 rate = rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rk3328_clk_get_rate()
1282 if (rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rkclk_init()
1286 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1288 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1329 rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rk3328_clk_probe()
[all …]
H A Dclk_rk322x.c109 old_rate = rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_armclk_set_clk()
137 return rockchip_pll_get_rate(&rk322x_pll_clks[APLL], priv->cru, APLL); in rk322x_armclk_set_clk()
586 rate = rockchip_pll_get_rate(&rk322x_pll_clks[clk->id - 1], in rk322x_clk_get_rate()
590 rate = rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_clk_get_rate()
957 if (rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rkclk_init()
961 priv->gpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
963 priv->cpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
1023 rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_clk_probe()
1028 rockchip_pll_get_rate(&rk322x_pll_clks[APLL], in rk322x_clk_probe()
H A Dclk_rk3562.c168 old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_armclk_set_rate()
1145 rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_vop_get_rate()
1363 rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_clk_get_rate()
1367 rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_get_rate()
1372 rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_get_rate()
1376 rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_get_rate()
1380 rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_get_rate()
1384 rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru, in rk3562_clk_get_rate()
1496 priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], in rk3562_clk_set_rate()
1502 priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_clk_set_rate()
[all …]
H A Dclk_rk3528.c210 old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL); in rk3528_armclk_set_clk()
1346 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, in rk3528_clk_get_rate()
1350 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_get_rate()
1354 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_get_rate()
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1363 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, in rk3528_clk_get_rate()
1471 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], in rk3528_clk_set_rate()
1477 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], in rk3528_clk_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
1859 rockchip_pll_get_rate(&rk3528_pll_clks[APLL], in rk3528_clk_init()
[all …]
H A Dclk_rk3568.c155 return rockchip_pll_get_rate(&rk3568_pll_clks[pll_id], in rk3568_pmu_pll_get_rate()
382 rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_get_rate()
386 rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_get_rate()
424 priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_set_rate()
430 priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_set_rate()
577 old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], in rk3568_armclk_set_clk()
1799 parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], in rk3568_dclk_vop_get_clk()
2516 rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru, in rk3568_clk_get_rate()
2520 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2524 rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_get_rate()
[all …]
H A Dclk_pll.su
H A Dclk_rv1106.c1052 rate = rockchip_pll_get_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_get_rate()
1056 rate = rockchip_pll_get_rate(&rv1106_pll_clks[DPLL], priv->cru, in rv1106_clk_get_rate()
1060 rate = rockchip_pll_get_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_get_rate()
1064 rate = rockchip_pll_get_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_get_rate()
1265 rockchip_pll_get_rate(&rv1106_pll_clks[APLL], in rv1106_clk_init()
H A Dclk_rv1126.c153 return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL], in rv1126_gpll_get_pmuclk()
573 old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], in rv1126_armclk_set_clk()
1625 rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, in rv1126_clk_get_rate()
1629 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1633 rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_get_rate()
1637 rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, in rv1126_clk_get_rate()
2136 rockchip_pll_get_rate(&rv1126_pll_clks[APLL], in rv1126_clk_init()
H A Dclk_pll.c567 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate() function
599 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h136 static inline ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate() function
160 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
/OK3568_Linux_fs/u-boot/spl/drivers/clk/rockchip/
H A Dclk_pll.su
/OK3568_Linux_fs/u-boot/spl/
H A Du-boot-spl.sym
H A Du-boot-spl.map
/OK3568_Linux_fs/u-boot/
H A DSystem.map
H A Du-boot.map
H A Du-boot.sym