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Searched refs:pll_mux (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c32 struct clk_mux pll_mux; member
567 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params() local
582 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
584 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
622 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
651 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_enable() local
657 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_enable()
666 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_disable() local
668 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_disable()
818 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params() local
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/OK3568_Linux_fs/kernel/drivers/clk/socfpga/
H A Dclk-s10.c15 static const struct clk_parent_data pll_mux[] = { variable
186 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
188 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
H A Dclk-agilex.c15 static const struct clk_parent_data pll_mux[] = { variable
228 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
230 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_10nm.c84 u8 pll_mux; member
549 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_pll_10nm_save_state()
553 cached->pix_clk_div, cached->pll_mux); in dsi_pll_10nm_save_state()
574 val |= cached->pll_mux; in dsi_pll_10nm_restore_state()
H A Ddsi_pll_7nm.c84 u8 pll_mux; member
575 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_pll_7nm_save_state()
579 cached->pix_clk_div, cached->pll_mux); in dsi_pll_7nm_save_state()
600 val |= cached->pll_mux; in dsi_pll_7nm_restore_state()