32 	struct clk_mux		pll_mux;  member
567 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_set_params()  local
582 		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3036_pll_set_params()
584 			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3036_pll_set_params()
622 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3036_pll_set_params()
651 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_enable()  local
657 	pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3036_pll_enable()
666 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_disable()  local
668 	pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3036_pll_disable()
818 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()  local
830 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3066_pll_set_params()
832 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3066_pll_set_params()
868 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3066_pll_set_params()
1081 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3399_pll_set_params()  local
1095 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3399_pll_set_params()
1097 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3399_pll_set_params()
1143 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3399_pll_set_params()
1366 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3588_pll_set_params()  local
1379 		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3588_pll_set_params()
1381 			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3588_pll_set_params()
1420 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3588_pll_set_params()
1455 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3588_pll_enable()  local
1461 	pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3588_pll_enable()
1470 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3588_pll_disable()  local
1472 	pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3588_pll_disable()
1635 	struct clk_mux *pll_mux;  in rockchip_clk_register_pll()  local
1654 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
1655 	pll_mux->reg = ctx->reg_base + mode_offset;  in rockchip_clk_register_pll()
1656 	pll_mux->shift = mode_shift;  in rockchip_clk_register_pll()
1658 		pll_mux->mask = PLL_RK3328_MODE_MASK;  in rockchip_clk_register_pll()
1660 		pll_mux->mask = PLL_MODE_MASK;  in rockchip_clk_register_pll()
1661 	pll_mux->flags = 0;  in rockchip_clk_register_pll()
1662 	pll_mux->lock = &ctx->lock;  in rockchip_clk_register_pll()
1663 	pll_mux->hw.init = &init;  in rockchip_clk_register_pll()
1664 	pll_mux->flags |= CLK_MUX_HIWORD_MASK;  in rockchip_clk_register_pll()
1680 	mux_clk = clk_register(NULL, &pll_mux->hw);  in rockchip_clk_register_pll()