Searched refs:nand0_clk_cfg (Results 1 – 7 of 7) sorted by relevance
47 u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ member
45 u32 nand0_clk_cfg; /* 0x80 nand clock control */ member
42 u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ member
45 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ member
548 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_deselect()
305 &ccm->nand0_clk_cfg); in sunxi_nfc_set_clk_rate()
275 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_clock_setup()