Searched refs:icsr (Results 1 – 5 of 5) sorted by relevance
20 u8 icsr; member78 if (bits & readb(&base->icsr)) in check_icsr_bits()89 clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); in check_stop()99 clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); in check_tend()103 clrbits_8(&base->icsr, SH_I2C_ICSR_TEND); in check_tend()213 clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); in i2c_raw_write()235 clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); in i2c_raw_read()247 clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); in i2c_raw_read()258 clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); in i2c_raw_read()
22 ureg(icsr);73 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte()84 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte_with_tack()86 if (SH_IC_TACK & readb(&dev->icsr)) in sh_irq_dte_with_tack()98 if (!(SH_IC_BUSY & readb(&dev->icsr))) in sh_irq_busy()126 clrbits_8(&dev->icsr, SH_IC_TACK); in sh_i2c_set_addr()142 writeb(0, &dev->icsr); in sh_i2c_finish()
33 unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ member
34 uint32_t icsr; /* Interrupt Control and State Register */ member
473 frame->icsr); in mcpcia_print_uncorrectable()