1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2015 6*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef ARMV7M_H 12*4882a593Smuzhiyun #define ARMV7M_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #if defined(__ASSEMBLY__) 15*4882a593Smuzhiyun .syntax unified 16*4882a593Smuzhiyun .thumb 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* armv7m fixed base addresses */ 20*4882a593Smuzhiyun #define V7M_SCS_BASE 0xE000E000 21*4882a593Smuzhiyun #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100) 22*4882a593Smuzhiyun #define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00) 23*4882a593Smuzhiyun #define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78) 24*4882a593Smuzhiyun #define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90) 25*4882a593Smuzhiyun #define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30) 26*4882a593Smuzhiyun #define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50) 27*4882a593Smuzhiyun #define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define V7M_SCB_VTOR 0x08 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #if !defined(__ASSEMBLY__) 32*4882a593Smuzhiyun struct v7m_scb { 33*4882a593Smuzhiyun uint32_t cpuid; /* CPUID Base Register */ 34*4882a593Smuzhiyun uint32_t icsr; /* Interrupt Control and State Register */ 35*4882a593Smuzhiyun uint32_t vtor; /* Vector Table Offset Register */ 36*4882a593Smuzhiyun uint32_t aircr; /* App Interrupt and Reset Control Register */ 37*4882a593Smuzhiyun uint32_t scr; /* offset 0x10: System Control Register */ 38*4882a593Smuzhiyun uint32_t ccr; /* offset 0x14: Config and Control Register */ 39*4882a593Smuzhiyun uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */ 40*4882a593Smuzhiyun uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */ 41*4882a593Smuzhiyun uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */ 42*4882a593Smuzhiyun uint32_t shcrs; /* offset 0x24: System Handler Control State */ 43*4882a593Smuzhiyun uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */ 44*4882a593Smuzhiyun uint32_t hfsr; /* offset 0x2C: HardFault Status Register */ 45*4882a593Smuzhiyun uint32_t res; /* offset 0x30: reserved */ 46*4882a593Smuzhiyun uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */ 47*4882a593Smuzhiyun uint32_t bfar; /* offset 0x38: BusFault Address Reg */ 48*4882a593Smuzhiyun uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun #define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define V7M_AIRCR_VECTKEY 0x5fa 53*4882a593Smuzhiyun #define V7M_AIRCR_VECTKEY_SHIFT 16 54*4882a593Smuzhiyun #define V7M_AIRCR_ENDIAN (1 << 15) 55*4882a593Smuzhiyun #define V7M_AIRCR_PRIGROUP_SHIFT 8 56*4882a593Smuzhiyun #define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) 57*4882a593Smuzhiyun #define V7M_AIRCR_SYSRESET (1 << 2) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define V7M_ICSR_VECTACT_MSK 0xFF 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define V7M_CCR_DCACHE 16 62*4882a593Smuzhiyun #define V7M_CCR_ICACHE 17 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct v7m_mpu { 65*4882a593Smuzhiyun uint32_t type; /* Type Register */ 66*4882a593Smuzhiyun uint32_t ctrl; /* Control Register */ 67*4882a593Smuzhiyun uint32_t rnr; /* Region Number Register */ 68*4882a593Smuzhiyun uint32_t rbar; /* Region Base Address Register */ 69*4882a593Smuzhiyun uint32_t rasr; /* Region Attribute and Size Register */ 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* !defined(__ASSEMBLY__) */ 74*4882a593Smuzhiyun #endif /* ARMV7M_H */ 75