1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ALPHA_MCE_H 3*4882a593Smuzhiyun #define __ALPHA_MCE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * This is the logout header that should be common to all platforms 7*4882a593Smuzhiyun * (assuming they are running OSF/1 PALcode, I guess). 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun struct el_common { 10*4882a593Smuzhiyun unsigned int size; /* size in bytes of logout area */ 11*4882a593Smuzhiyun unsigned int sbz1 : 30; /* should be zero */ 12*4882a593Smuzhiyun unsigned int err2 : 1; /* second error */ 13*4882a593Smuzhiyun unsigned int retry : 1; /* retry flag */ 14*4882a593Smuzhiyun unsigned int proc_offset; /* processor-specific offset */ 15*4882a593Smuzhiyun unsigned int sys_offset; /* system-specific offset */ 16*4882a593Smuzhiyun unsigned int code; /* machine check code */ 17*4882a593Smuzhiyun unsigned int frame_rev; /* frame revision */ 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Machine Check Frame for uncorrectable errors (Large format) 21*4882a593Smuzhiyun * --- This is used to log uncorrectable errors such as 22*4882a593Smuzhiyun * double bit ECC errors. 23*4882a593Smuzhiyun * --- These errors are detected by both processor and systems. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun struct el_common_EV5_uncorrectable_mcheck { 26*4882a593Smuzhiyun unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */ 27*4882a593Smuzhiyun unsigned long paltemp[24]; /* PAL TEMP REGS. */ 28*4882a593Smuzhiyun unsigned long exc_addr; /* Address of excepting instruction*/ 29*4882a593Smuzhiyun unsigned long exc_sum; /* Summary of arithmetic traps. */ 30*4882a593Smuzhiyun unsigned long exc_mask; /* Exception mask (from exc_sum). */ 31*4882a593Smuzhiyun unsigned long pal_base; /* Base address for PALcode. */ 32*4882a593Smuzhiyun unsigned long isr; /* Interrupt Status Reg. */ 33*4882a593Smuzhiyun unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ 34*4882a593Smuzhiyun unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity 35*4882a593Smuzhiyun <12> set TAG parity*/ 36*4882a593Smuzhiyun unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1: 37*4882a593Smuzhiyun <2> Data error in bank 0 38*4882a593Smuzhiyun <3> Data error in bank 1 39*4882a593Smuzhiyun <4> Tag error in bank 0 40*4882a593Smuzhiyun <5> Tag error in bank 1 */ 41*4882a593Smuzhiyun unsigned long va; /* Effective VA of fault or miss. */ 42*4882a593Smuzhiyun unsigned long mm_stat; /* Holds the reason for D-stream 43*4882a593Smuzhiyun fault or D-cache parity errors */ 44*4882a593Smuzhiyun unsigned long sc_addr; /* Address that was being accessed 45*4882a593Smuzhiyun when EV5 detected Secondary cache 46*4882a593Smuzhiyun failure. */ 47*4882a593Smuzhiyun unsigned long sc_stat; /* Helps determine if the error was 48*4882a593Smuzhiyun TAG/Data parity(Secondary Cache)*/ 49*4882a593Smuzhiyun unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ 50*4882a593Smuzhiyun unsigned long ei_addr; /* Physical address of any transfer 51*4882a593Smuzhiyun that is logged in EV5 EI_STAT */ 52*4882a593Smuzhiyun unsigned long fill_syndrome; /* For correcting ECC errors. */ 53*4882a593Smuzhiyun unsigned long ei_stat; /* Helps identify reason of any 54*4882a593Smuzhiyun processor uncorrectable error 55*4882a593Smuzhiyun at its external interface. */ 56*4882a593Smuzhiyun unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/ 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct el_common_EV6_mcheck { 60*4882a593Smuzhiyun unsigned int FrameSize; /* Bytes, including this field */ 61*4882a593Smuzhiyun unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */ 62*4882a593Smuzhiyun unsigned int CpuOffset; /* Offset to CPU-specific info */ 63*4882a593Smuzhiyun unsigned int SystemOffset; /* Offset to system-specific info */ 64*4882a593Smuzhiyun unsigned int MCHK_Code; 65*4882a593Smuzhiyun unsigned int MCHK_Frame_Rev; 66*4882a593Smuzhiyun unsigned long I_STAT; /* EV6 Internal Processor Registers */ 67*4882a593Smuzhiyun unsigned long DC_STAT; /* (See the 21264 Spec) */ 68*4882a593Smuzhiyun unsigned long C_ADDR; 69*4882a593Smuzhiyun unsigned long DC1_SYNDROME; 70*4882a593Smuzhiyun unsigned long DC0_SYNDROME; 71*4882a593Smuzhiyun unsigned long C_STAT; 72*4882a593Smuzhiyun unsigned long C_STS; 73*4882a593Smuzhiyun unsigned long MM_STAT; 74*4882a593Smuzhiyun unsigned long EXC_ADDR; 75*4882a593Smuzhiyun unsigned long IER_CM; 76*4882a593Smuzhiyun unsigned long ISUM; 77*4882a593Smuzhiyun unsigned long RESERVED0; 78*4882a593Smuzhiyun unsigned long PAL_BASE; 79*4882a593Smuzhiyun unsigned long I_CTL; 80*4882a593Smuzhiyun unsigned long PCTX; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* __ALPHA_MCE_H */ 85