Searched refs:dramtmg5 (Results 1 – 6 of 6) sorted by relevance
90 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ member
126 u32 dramtmg5; /* 0x114 */ member
150 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
186 &mctl_ctl->dramtmg5); in mctl_init()
182 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()