Searched refs:div_fsys1 (Results 1 – 6 of 6) sorted by relevance
409 div = sub_div = readl(&clk->div_fsys1); in exynos5_get_periph_rate()503 div = readl(&clk->div_fsys1); in exynos542x_get_periph_rate()807 ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()808 pre_ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()849 addr = (unsigned int)&clk->div_fsys1; in exynos4_set_mmc_clk()882 addr = (unsigned int)&clk->div_fsys1; in exynos5_set_mmc_clk()906 addr = (unsigned int)&clk->div_fsys1; in exynos5420_set_mmc_clk()
69 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()
945 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()1002 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; in emmc_boot_clk_div_set()1004 writel(div_mmc, (unsigned int) &clk->div_fsys1); in emmc_boot_clk_div_set()
96 unsigned int div_fsys1; member333 unsigned int div_fsys1; member724 unsigned int div_fsys1; member1132 unsigned int div_fsys1; member
316 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init()
332 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); in board_clock_init()