Searched refs:ddr_mode (Results 1 – 9 of 9) sorted by relevance
783 MV_DRAM_MODES *ddr_mode; in ddr3_static_training_init() local787 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_training_init()790 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()792 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()793 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()795 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()883 MV_DRAM_MODES *ddr_mode; in ddr3_static_mc_init() local887 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_mc_init()889 while (ddr_mode->regs[j].reg_addr != 0) { in ddr3_static_mc_init()890 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()[all …]
43 enum ddr_mode mem_type; /* Type of on-board memory */
431 enum ddr_mode { enum
41 enum ddr_mode mem_type; /* Memory type */
76 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll()
487 static void clock_get_mem_selection(enum ddr_mode *mem_type, in clock_get_mem_selection()504 enum ddr_mode mem_type; in get_arm_ratios()528 enum ddr_mode mem_type; in clock_get_mem_timings()
946 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
48 bool ddr_mode; member1042 unsigned char timing, bool *ddr_mode) in sd_set_timing() argument1047 *ddr_mode = false; in sd_set_timing()1062 *ddr_mode = true; in sd_set_timing()1115 sd_set_timing(host, ios->timing, &host->ddr_mode); in sdmmc_set_ios()1246 if (!host->ddr_mode) in sdmmc_execute_tuning()
537 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; in set_sysctl()