1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Clock initialization routines 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __EXYNOS_CLOCK_INIT_H 10*4882a593Smuzhiyun #define __EXYNOS_CLOCK_INIT_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum { 13*4882a593Smuzhiyun #ifdef CONFIG_EXYNOS5420 14*4882a593Smuzhiyun MEM_TIMINGS_MSR_COUNT = 5, 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun MEM_TIMINGS_MSR_COUNT = 4, 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* These are the ratio's for configuring ARM clock */ 21*4882a593Smuzhiyun struct arm_clk_ratios { 22*4882a593Smuzhiyun unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun unsigned apll_mdiv; 25*4882a593Smuzhiyun unsigned apll_pdiv; 26*4882a593Smuzhiyun unsigned apll_sdiv; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun unsigned arm2_ratio; 29*4882a593Smuzhiyun unsigned apll_ratio; 30*4882a593Smuzhiyun unsigned pclk_dbg_ratio; 31*4882a593Smuzhiyun unsigned atb_ratio; 32*4882a593Smuzhiyun unsigned periph_ratio; 33*4882a593Smuzhiyun unsigned acp_ratio; 34*4882a593Smuzhiyun unsigned cpud_ratio; 35*4882a593Smuzhiyun unsigned arm_ratio; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* These are the memory timings for a particular memory type and speed */ 39*4882a593Smuzhiyun struct mem_timings { 40*4882a593Smuzhiyun enum mem_manuf mem_manuf; /* Memory manufacturer */ 41*4882a593Smuzhiyun enum ddr_mode mem_type; /* Memory type */ 42*4882a593Smuzhiyun unsigned frequency_mhz; /* Frequency of memory in MHz */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Here follow the timing parameters for the selected memory */ 45*4882a593Smuzhiyun unsigned apll_mdiv; 46*4882a593Smuzhiyun unsigned apll_pdiv; 47*4882a593Smuzhiyun unsigned apll_sdiv; 48*4882a593Smuzhiyun unsigned mpll_mdiv; 49*4882a593Smuzhiyun unsigned mpll_pdiv; 50*4882a593Smuzhiyun unsigned mpll_sdiv; 51*4882a593Smuzhiyun unsigned cpll_mdiv; 52*4882a593Smuzhiyun unsigned cpll_pdiv; 53*4882a593Smuzhiyun unsigned cpll_sdiv; 54*4882a593Smuzhiyun unsigned gpll_mdiv; 55*4882a593Smuzhiyun unsigned gpll_pdiv; 56*4882a593Smuzhiyun unsigned gpll_sdiv; 57*4882a593Smuzhiyun unsigned epll_mdiv; 58*4882a593Smuzhiyun unsigned epll_pdiv; 59*4882a593Smuzhiyun unsigned epll_sdiv; 60*4882a593Smuzhiyun unsigned vpll_mdiv; 61*4882a593Smuzhiyun unsigned vpll_pdiv; 62*4882a593Smuzhiyun unsigned vpll_sdiv; 63*4882a593Smuzhiyun unsigned bpll_mdiv; 64*4882a593Smuzhiyun unsigned bpll_pdiv; 65*4882a593Smuzhiyun unsigned bpll_sdiv; 66*4882a593Smuzhiyun unsigned kpll_mdiv; 67*4882a593Smuzhiyun unsigned kpll_pdiv; 68*4882a593Smuzhiyun unsigned kpll_sdiv; 69*4882a593Smuzhiyun unsigned dpll_mdiv; 70*4882a593Smuzhiyun unsigned dpll_pdiv; 71*4882a593Smuzhiyun unsigned dpll_sdiv; 72*4882a593Smuzhiyun unsigned ipll_mdiv; 73*4882a593Smuzhiyun unsigned ipll_pdiv; 74*4882a593Smuzhiyun unsigned ipll_sdiv; 75*4882a593Smuzhiyun unsigned spll_mdiv; 76*4882a593Smuzhiyun unsigned spll_pdiv; 77*4882a593Smuzhiyun unsigned spll_sdiv; 78*4882a593Smuzhiyun unsigned rpll_mdiv; 79*4882a593Smuzhiyun unsigned rpll_pdiv; 80*4882a593Smuzhiyun unsigned rpll_sdiv; 81*4882a593Smuzhiyun unsigned pclk_cdrex_ratio; 82*4882a593Smuzhiyun unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun unsigned timing_ref; 85*4882a593Smuzhiyun unsigned timing_row; 86*4882a593Smuzhiyun unsigned timing_data; 87*4882a593Smuzhiyun unsigned timing_power; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* DQS, DQ, DEBUG offsets */ 90*4882a593Smuzhiyun unsigned phy0_dqs; 91*4882a593Smuzhiyun unsigned phy1_dqs; 92*4882a593Smuzhiyun unsigned phy0_dq; 93*4882a593Smuzhiyun unsigned phy1_dq; 94*4882a593Smuzhiyun unsigned phy0_tFS; 95*4882a593Smuzhiyun unsigned phy1_tFS; 96*4882a593Smuzhiyun unsigned phy0_pulld_dqs; 97*4882a593Smuzhiyun unsigned phy1_pulld_dqs; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun unsigned lpddr3_ctrl_phy_reset; 100*4882a593Smuzhiyun unsigned ctrl_start_point; 101*4882a593Smuzhiyun unsigned ctrl_inc; 102*4882a593Smuzhiyun unsigned ctrl_start; 103*4882a593Smuzhiyun unsigned ctrl_dll_on; 104*4882a593Smuzhiyun unsigned ctrl_ref; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun unsigned ctrl_force; 107*4882a593Smuzhiyun unsigned ctrl_rdlat; 108*4882a593Smuzhiyun unsigned ctrl_bstlen; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun unsigned fp_resync; 111*4882a593Smuzhiyun unsigned iv_size; 112*4882a593Smuzhiyun unsigned dfi_init_start; 113*4882a593Smuzhiyun unsigned aref_en; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun unsigned rd_fetch; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun unsigned zq_mode_dds; 118*4882a593Smuzhiyun unsigned zq_mode_term; 119*4882a593Smuzhiyun unsigned zq_mode_noterm; /* 1 to allow termination disable */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun unsigned memcontrol; 122*4882a593Smuzhiyun unsigned memconfig; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun unsigned membaseconfig0; 125*4882a593Smuzhiyun unsigned membaseconfig1; 126*4882a593Smuzhiyun unsigned prechconfig_tp_cnt; 127*4882a593Smuzhiyun unsigned dpwrdn_cyc; 128*4882a593Smuzhiyun unsigned dsref_cyc; 129*4882a593Smuzhiyun unsigned concontrol; 130*4882a593Smuzhiyun /* Channel and Chip Selection */ 131*4882a593Smuzhiyun uint8_t dmc_channels; /* number of memory channels */ 132*4882a593Smuzhiyun uint8_t chips_per_channel; /* number of chips per channel */ 133*4882a593Smuzhiyun uint8_t chips_to_configure; /* number of chips to configure */ 134*4882a593Smuzhiyun uint8_t send_zq_init; /* 1 to send this command */ 135*4882a593Smuzhiyun unsigned impedance; /* drive strength impedeance */ 136*4882a593Smuzhiyun uint8_t gate_leveling_enable; /* check gate leveling is enabled */ 137*4882a593Smuzhiyun uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /** 141*4882a593Smuzhiyun * Get the correct memory timings for our selected memory type and speed. 142*4882a593Smuzhiyun * 143*4882a593Smuzhiyun * This function can be called from SPL or the main U-Boot. 144*4882a593Smuzhiyun * 145*4882a593Smuzhiyun * @return pointer to the memory timings that we should use 146*4882a593Smuzhiyun */ 147*4882a593Smuzhiyun struct mem_timings *clock_get_mem_timings(void); 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * Initialize clock for the device 151*4882a593Smuzhiyun */ 152*4882a593Smuzhiyun void system_clock_init(void); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * Set clock divisor value for booting from EMMC. 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun void emmc_boot_clk_div_set(void); 158*4882a593Smuzhiyun #endif 159