1*4882a593Smuzhiyun #ifndef __DMC_H__ 2*4882a593Smuzhiyun #define __DMC_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 5*4882a593Smuzhiyun struct exynos4_dmc { 6*4882a593Smuzhiyun unsigned int concontrol; 7*4882a593Smuzhiyun unsigned int memcontrol; 8*4882a593Smuzhiyun unsigned int memconfig0; 9*4882a593Smuzhiyun unsigned int memconfig1; 10*4882a593Smuzhiyun unsigned int directcmd; 11*4882a593Smuzhiyun unsigned int prechconfig; 12*4882a593Smuzhiyun unsigned int phycontrol0; 13*4882a593Smuzhiyun unsigned int phycontrol1; 14*4882a593Smuzhiyun unsigned int phycontrol2; 15*4882a593Smuzhiyun unsigned int phycontrol3; 16*4882a593Smuzhiyun unsigned int pwrdnconfig; 17*4882a593Smuzhiyun unsigned char res1[0x4]; 18*4882a593Smuzhiyun unsigned int timingref; 19*4882a593Smuzhiyun unsigned int timingrow; 20*4882a593Smuzhiyun unsigned int timingdata; 21*4882a593Smuzhiyun unsigned int timingpower; 22*4882a593Smuzhiyun unsigned int phystatus; 23*4882a593Smuzhiyun unsigned int phyzqcontrol; 24*4882a593Smuzhiyun unsigned int chip0status; 25*4882a593Smuzhiyun unsigned int chip1status; 26*4882a593Smuzhiyun unsigned int arefstatus; 27*4882a593Smuzhiyun unsigned int mrstatus; 28*4882a593Smuzhiyun unsigned int phytest0; 29*4882a593Smuzhiyun unsigned int phytest1; 30*4882a593Smuzhiyun unsigned int qoscontrol0; 31*4882a593Smuzhiyun unsigned int qosconfig0; 32*4882a593Smuzhiyun unsigned int qoscontrol1; 33*4882a593Smuzhiyun unsigned int qosconfig1; 34*4882a593Smuzhiyun unsigned int qoscontrol2; 35*4882a593Smuzhiyun unsigned int qosconfig2; 36*4882a593Smuzhiyun unsigned int qoscontrol3; 37*4882a593Smuzhiyun unsigned int qosconfig3; 38*4882a593Smuzhiyun unsigned int qoscontrol4; 39*4882a593Smuzhiyun unsigned int qosconfig4; 40*4882a593Smuzhiyun unsigned int qoscontrol5; 41*4882a593Smuzhiyun unsigned int qosconfig5; 42*4882a593Smuzhiyun unsigned int qoscontrol6; 43*4882a593Smuzhiyun unsigned int qosconfig6; 44*4882a593Smuzhiyun unsigned int qoscontrol7; 45*4882a593Smuzhiyun unsigned int qosconfig7; 46*4882a593Smuzhiyun unsigned int qoscontrol8; 47*4882a593Smuzhiyun unsigned int qosconfig8; 48*4882a593Smuzhiyun unsigned int qoscontrol9; 49*4882a593Smuzhiyun unsigned int qosconfig9; 50*4882a593Smuzhiyun unsigned int qoscontrol10; 51*4882a593Smuzhiyun unsigned int qosconfig10; 52*4882a593Smuzhiyun unsigned int qoscontrol11; 53*4882a593Smuzhiyun unsigned int qosconfig11; 54*4882a593Smuzhiyun unsigned int qoscontrol12; 55*4882a593Smuzhiyun unsigned int qosconfig12; 56*4882a593Smuzhiyun unsigned int qoscontrol13; 57*4882a593Smuzhiyun unsigned int qosconfig13; 58*4882a593Smuzhiyun unsigned int qoscontrol14; 59*4882a593Smuzhiyun unsigned int qosconfig14; 60*4882a593Smuzhiyun unsigned int qoscontrol15; 61*4882a593Smuzhiyun unsigned int qosconfig15; 62*4882a593Smuzhiyun unsigned int qostimeout0; 63*4882a593Smuzhiyun unsigned int qostimeout1; 64*4882a593Smuzhiyun unsigned char res2[0x8]; 65*4882a593Smuzhiyun unsigned int ivcontrol; 66*4882a593Smuzhiyun unsigned char res3[0x8]; 67*4882a593Smuzhiyun unsigned int perevconfig; 68*4882a593Smuzhiyun unsigned char res4[0xDF00]; 69*4882a593Smuzhiyun unsigned int pmnc_ppc_a; 70*4882a593Smuzhiyun unsigned char res5[0xC]; 71*4882a593Smuzhiyun unsigned int cntens_ppc_a; 72*4882a593Smuzhiyun unsigned char res6[0xC]; 73*4882a593Smuzhiyun unsigned int cntenc_ppc_a; 74*4882a593Smuzhiyun unsigned char res7[0xC]; 75*4882a593Smuzhiyun unsigned int intens_ppc_a; 76*4882a593Smuzhiyun unsigned char res8[0xC]; 77*4882a593Smuzhiyun unsigned int intenc_ppc_a; 78*4882a593Smuzhiyun unsigned char res9[0xC]; 79*4882a593Smuzhiyun unsigned int flag_ppc_a; 80*4882a593Smuzhiyun unsigned char res10[0xAC]; 81*4882a593Smuzhiyun unsigned int ccnt_ppc_a; 82*4882a593Smuzhiyun unsigned char res11[0xC]; 83*4882a593Smuzhiyun unsigned int pmcnt0_ppc_a; 84*4882a593Smuzhiyun unsigned char res12[0xC]; 85*4882a593Smuzhiyun unsigned int pmcnt1_ppc_a; 86*4882a593Smuzhiyun unsigned char res13[0xC]; 87*4882a593Smuzhiyun unsigned int pmcnt2_ppc_a; 88*4882a593Smuzhiyun unsigned char res14[0xC]; 89*4882a593Smuzhiyun unsigned int pmcnt3_ppc_a; 90*4882a593Smuzhiyun unsigned char res15[0xEBC]; 91*4882a593Smuzhiyun unsigned int pmnc_ppc_m; 92*4882a593Smuzhiyun unsigned char res16[0xC]; 93*4882a593Smuzhiyun unsigned int cntens_ppc_m; 94*4882a593Smuzhiyun unsigned char res17[0xC]; 95*4882a593Smuzhiyun unsigned int cntenc_ppc_m; 96*4882a593Smuzhiyun unsigned char res18[0xC]; 97*4882a593Smuzhiyun unsigned int intens_ppc_m; 98*4882a593Smuzhiyun unsigned char res19[0xC]; 99*4882a593Smuzhiyun unsigned int intenc_ppc_m; 100*4882a593Smuzhiyun unsigned char res20[0xC]; 101*4882a593Smuzhiyun unsigned int flag_ppc_m; 102*4882a593Smuzhiyun unsigned char res21[0xAC]; 103*4882a593Smuzhiyun unsigned int ccnt_ppc_m; 104*4882a593Smuzhiyun unsigned char res22[0xC]; 105*4882a593Smuzhiyun unsigned int pmcnt0_ppc_m; 106*4882a593Smuzhiyun unsigned char res23[0xC]; 107*4882a593Smuzhiyun unsigned int pmcnt1_ppc_m; 108*4882a593Smuzhiyun unsigned char res24[0xC]; 109*4882a593Smuzhiyun unsigned int pmcnt2_ppc_m; 110*4882a593Smuzhiyun unsigned char res25[0xC]; 111*4882a593Smuzhiyun unsigned int pmcnt3_ppc_m; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct exynos5_dmc { 115*4882a593Smuzhiyun unsigned int concontrol; 116*4882a593Smuzhiyun unsigned int memcontrol; 117*4882a593Smuzhiyun unsigned int memconfig0; 118*4882a593Smuzhiyun unsigned int memconfig1; 119*4882a593Smuzhiyun unsigned int directcmd; 120*4882a593Smuzhiyun unsigned int prechconfig; 121*4882a593Smuzhiyun unsigned int phycontrol0; 122*4882a593Smuzhiyun unsigned char res1[0xc]; 123*4882a593Smuzhiyun unsigned int pwrdnconfig; 124*4882a593Smuzhiyun unsigned int timingpzq; 125*4882a593Smuzhiyun unsigned int timingref; 126*4882a593Smuzhiyun unsigned int timingrow; 127*4882a593Smuzhiyun unsigned int timingdata; 128*4882a593Smuzhiyun unsigned int timingpower; 129*4882a593Smuzhiyun unsigned int phystatus; 130*4882a593Smuzhiyun unsigned char res2[0x4]; 131*4882a593Smuzhiyun unsigned int chipstatus_ch0; 132*4882a593Smuzhiyun unsigned int chipstatus_ch1; 133*4882a593Smuzhiyun unsigned char res3[0x4]; 134*4882a593Smuzhiyun unsigned int mrstatus; 135*4882a593Smuzhiyun unsigned char res4[0x8]; 136*4882a593Smuzhiyun unsigned int qoscontrol0; 137*4882a593Smuzhiyun unsigned char resr5[0x4]; 138*4882a593Smuzhiyun unsigned int qoscontrol1; 139*4882a593Smuzhiyun unsigned char res6[0x4]; 140*4882a593Smuzhiyun unsigned int qoscontrol2; 141*4882a593Smuzhiyun unsigned char res7[0x4]; 142*4882a593Smuzhiyun unsigned int qoscontrol3; 143*4882a593Smuzhiyun unsigned char res8[0x4]; 144*4882a593Smuzhiyun unsigned int qoscontrol4; 145*4882a593Smuzhiyun unsigned char res9[0x4]; 146*4882a593Smuzhiyun unsigned int qoscontrol5; 147*4882a593Smuzhiyun unsigned char res10[0x4]; 148*4882a593Smuzhiyun unsigned int qoscontrol6; 149*4882a593Smuzhiyun unsigned char res11[0x4]; 150*4882a593Smuzhiyun unsigned int qoscontrol7; 151*4882a593Smuzhiyun unsigned char res12[0x4]; 152*4882a593Smuzhiyun unsigned int qoscontrol8; 153*4882a593Smuzhiyun unsigned char res13[0x4]; 154*4882a593Smuzhiyun unsigned int qoscontrol9; 155*4882a593Smuzhiyun unsigned char res14[0x4]; 156*4882a593Smuzhiyun unsigned int qoscontrol10; 157*4882a593Smuzhiyun unsigned char res15[0x4]; 158*4882a593Smuzhiyun unsigned int qoscontrol11; 159*4882a593Smuzhiyun unsigned char res16[0x4]; 160*4882a593Smuzhiyun unsigned int qoscontrol12; 161*4882a593Smuzhiyun unsigned char res17[0x4]; 162*4882a593Smuzhiyun unsigned int qoscontrol13; 163*4882a593Smuzhiyun unsigned char res18[0x4]; 164*4882a593Smuzhiyun unsigned int qoscontrol14; 165*4882a593Smuzhiyun unsigned char res19[0x4]; 166*4882a593Smuzhiyun unsigned int qoscontrol15; 167*4882a593Smuzhiyun unsigned char res20[0x14]; 168*4882a593Smuzhiyun unsigned int ivcontrol; 169*4882a593Smuzhiyun unsigned int wrtra_config; 170*4882a593Smuzhiyun unsigned int rdlvl_config; 171*4882a593Smuzhiyun unsigned char res21[0x8]; 172*4882a593Smuzhiyun unsigned int brbrsvconfig; 173*4882a593Smuzhiyun unsigned int brbqosconfig; 174*4882a593Smuzhiyun unsigned int membaseconfig0; 175*4882a593Smuzhiyun unsigned int membaseconfig1; 176*4882a593Smuzhiyun unsigned char res22[0xc]; 177*4882a593Smuzhiyun unsigned int wrlvl_config; 178*4882a593Smuzhiyun unsigned char res23[0xc]; 179*4882a593Smuzhiyun unsigned int perevcontrol; 180*4882a593Smuzhiyun unsigned int perev0config; 181*4882a593Smuzhiyun unsigned int perev1config; 182*4882a593Smuzhiyun unsigned int perev2config; 183*4882a593Smuzhiyun unsigned int perev3config; 184*4882a593Smuzhiyun unsigned char res24[0xdebc]; 185*4882a593Smuzhiyun unsigned int pmnc_ppc_a; 186*4882a593Smuzhiyun unsigned char res25[0xc]; 187*4882a593Smuzhiyun unsigned int cntens_ppc_a; 188*4882a593Smuzhiyun unsigned char res26[0xc]; 189*4882a593Smuzhiyun unsigned int cntenc_ppc_a; 190*4882a593Smuzhiyun unsigned char res27[0xc]; 191*4882a593Smuzhiyun unsigned int intens_ppc_a; 192*4882a593Smuzhiyun unsigned char res28[0xc]; 193*4882a593Smuzhiyun unsigned int intenc_ppc_a; 194*4882a593Smuzhiyun unsigned char res29[0xc]; 195*4882a593Smuzhiyun unsigned int flag_ppc_a; 196*4882a593Smuzhiyun unsigned char res30[0xac]; 197*4882a593Smuzhiyun unsigned int ccnt_ppc_a; 198*4882a593Smuzhiyun unsigned char res31[0xc]; 199*4882a593Smuzhiyun unsigned int pmcnt0_ppc_a; 200*4882a593Smuzhiyun unsigned char res32[0xc]; 201*4882a593Smuzhiyun unsigned int pmcnt1_ppc_a; 202*4882a593Smuzhiyun unsigned char res33[0xc]; 203*4882a593Smuzhiyun unsigned int pmcnt2_ppc_a; 204*4882a593Smuzhiyun unsigned char res34[0xc]; 205*4882a593Smuzhiyun unsigned int pmcnt3_ppc_a; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun struct exynos5420_dmc { 209*4882a593Smuzhiyun unsigned int concontrol; 210*4882a593Smuzhiyun unsigned int memcontrol; 211*4882a593Smuzhiyun unsigned int cgcontrol; 212*4882a593Smuzhiyun unsigned char res500[0x4]; 213*4882a593Smuzhiyun unsigned int directcmd; 214*4882a593Smuzhiyun unsigned int prechconfig0; 215*4882a593Smuzhiyun unsigned int phycontrol0; 216*4882a593Smuzhiyun unsigned int prechconfig1; 217*4882a593Smuzhiyun unsigned char res1[0x8]; 218*4882a593Smuzhiyun unsigned int pwrdnconfig; 219*4882a593Smuzhiyun unsigned int timingpzq; 220*4882a593Smuzhiyun unsigned int timingref; 221*4882a593Smuzhiyun unsigned int timingrow0; 222*4882a593Smuzhiyun unsigned int timingdata0; 223*4882a593Smuzhiyun unsigned int timingpower0; 224*4882a593Smuzhiyun unsigned int phystatus; 225*4882a593Smuzhiyun unsigned int etctiming; 226*4882a593Smuzhiyun unsigned int chipstatus; 227*4882a593Smuzhiyun unsigned char res3[0x8]; 228*4882a593Smuzhiyun unsigned int mrstatus; 229*4882a593Smuzhiyun unsigned char res4[0x8]; 230*4882a593Smuzhiyun unsigned int qoscontrol0; 231*4882a593Smuzhiyun unsigned char resr5[0x4]; 232*4882a593Smuzhiyun unsigned int qoscontrol1; 233*4882a593Smuzhiyun unsigned char res6[0x4]; 234*4882a593Smuzhiyun unsigned int qoscontrol2; 235*4882a593Smuzhiyun unsigned char res7[0x4]; 236*4882a593Smuzhiyun unsigned int qoscontrol3; 237*4882a593Smuzhiyun unsigned char res8[0x4]; 238*4882a593Smuzhiyun unsigned int qoscontrol4; 239*4882a593Smuzhiyun unsigned char res9[0x4]; 240*4882a593Smuzhiyun unsigned int qoscontrol5; 241*4882a593Smuzhiyun unsigned char res10[0x4]; 242*4882a593Smuzhiyun unsigned int qoscontrol6; 243*4882a593Smuzhiyun unsigned char res11[0x4]; 244*4882a593Smuzhiyun unsigned int qoscontrol7; 245*4882a593Smuzhiyun unsigned char res12[0x4]; 246*4882a593Smuzhiyun unsigned int qoscontrol8; 247*4882a593Smuzhiyun unsigned char res13[0x4]; 248*4882a593Smuzhiyun unsigned int qoscontrol9; 249*4882a593Smuzhiyun unsigned char res14[0x4]; 250*4882a593Smuzhiyun unsigned int qoscontrol10; 251*4882a593Smuzhiyun unsigned char res15[0x4]; 252*4882a593Smuzhiyun unsigned int qoscontrol11; 253*4882a593Smuzhiyun unsigned char res16[0x4]; 254*4882a593Smuzhiyun unsigned int qoscontrol12; 255*4882a593Smuzhiyun unsigned char res17[0x4]; 256*4882a593Smuzhiyun unsigned int qoscontrol13; 257*4882a593Smuzhiyun unsigned char res18[0x4]; 258*4882a593Smuzhiyun unsigned int qoscontrol14; 259*4882a593Smuzhiyun unsigned char res19[0x4]; 260*4882a593Smuzhiyun unsigned int qoscontrol15; 261*4882a593Smuzhiyun unsigned char res20[0x4]; 262*4882a593Smuzhiyun unsigned int timing_set_sw; 263*4882a593Smuzhiyun unsigned int timingrow1; 264*4882a593Smuzhiyun unsigned int timingdata1; 265*4882a593Smuzhiyun unsigned int timingpower1; 266*4882a593Smuzhiyun unsigned char res300[0x4]; 267*4882a593Smuzhiyun unsigned int wrtra_config; 268*4882a593Smuzhiyun unsigned int rdlvl_config; 269*4882a593Smuzhiyun unsigned char res21[0x4]; 270*4882a593Smuzhiyun unsigned int brbrsvcontrol; 271*4882a593Smuzhiyun unsigned int brbrsvconfig; 272*4882a593Smuzhiyun unsigned int brbqosconfig; 273*4882a593Smuzhiyun unsigned char res301[0x14]; 274*4882a593Smuzhiyun unsigned int wrlvl_config0; 275*4882a593Smuzhiyun unsigned int wrlvl_config1; 276*4882a593Smuzhiyun unsigned int wrlvl_status; 277*4882a593Smuzhiyun unsigned char res23[0x4]; 278*4882a593Smuzhiyun unsigned int ppcclockon; 279*4882a593Smuzhiyun unsigned int perevconfig0; 280*4882a593Smuzhiyun unsigned int perevconfig1; 281*4882a593Smuzhiyun unsigned int perevconfig2; 282*4882a593Smuzhiyun unsigned int perevconfig3; 283*4882a593Smuzhiyun unsigned char res24[0xc]; 284*4882a593Smuzhiyun unsigned int control_io_rdata; 285*4882a593Smuzhiyun unsigned char res240[0xc]; 286*4882a593Smuzhiyun unsigned int cacal_config0; 287*4882a593Smuzhiyun unsigned int cacal_config1; 288*4882a593Smuzhiyun unsigned int cacal_status; 289*4882a593Smuzhiyun unsigned char res302[0xa4]; 290*4882a593Smuzhiyun unsigned int bp_control0; 291*4882a593Smuzhiyun unsigned int bp_config0_r; 292*4882a593Smuzhiyun unsigned int bp_config0_w; 293*4882a593Smuzhiyun unsigned char res303[0x4]; 294*4882a593Smuzhiyun unsigned int bp_control1; 295*4882a593Smuzhiyun unsigned int bp_config1_r; 296*4882a593Smuzhiyun unsigned int bp_config1_w; 297*4882a593Smuzhiyun unsigned char res304[0x4]; 298*4882a593Smuzhiyun unsigned int bp_control2; 299*4882a593Smuzhiyun unsigned int bp_config2_r; 300*4882a593Smuzhiyun unsigned int bp_config2_w; 301*4882a593Smuzhiyun unsigned char res305[0x4]; 302*4882a593Smuzhiyun unsigned int bp_control3; 303*4882a593Smuzhiyun unsigned int bp_config3_r; 304*4882a593Smuzhiyun unsigned int bp_config3_w; 305*4882a593Smuzhiyun unsigned char res306[0xddb4]; 306*4882a593Smuzhiyun unsigned int pmnc_ppc; 307*4882a593Smuzhiyun unsigned char res25[0xc]; 308*4882a593Smuzhiyun unsigned int cntens_ppc; 309*4882a593Smuzhiyun unsigned char res26[0xc]; 310*4882a593Smuzhiyun unsigned int cntenc_ppc; 311*4882a593Smuzhiyun unsigned char res27[0xc]; 312*4882a593Smuzhiyun unsigned int intens_ppc; 313*4882a593Smuzhiyun unsigned char res28[0xc]; 314*4882a593Smuzhiyun unsigned int intenc_ppc; 315*4882a593Smuzhiyun unsigned char res29[0xc]; 316*4882a593Smuzhiyun unsigned int flag_ppc; 317*4882a593Smuzhiyun unsigned char res30[0xac]; 318*4882a593Smuzhiyun unsigned int ccnt_ppc; 319*4882a593Smuzhiyun unsigned char res31[0xc]; 320*4882a593Smuzhiyun unsigned int pmcnt0_ppc; 321*4882a593Smuzhiyun unsigned char res32[0xc]; 322*4882a593Smuzhiyun unsigned int pmcnt1_ppc; 323*4882a593Smuzhiyun unsigned char res33[0xc]; 324*4882a593Smuzhiyun unsigned int pmcnt2_ppc; 325*4882a593Smuzhiyun unsigned char res34[0xc]; 326*4882a593Smuzhiyun unsigned int pmcnt3_ppc; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun struct exynos5_phy_control { 330*4882a593Smuzhiyun unsigned int phy_con0; 331*4882a593Smuzhiyun unsigned int phy_con1; 332*4882a593Smuzhiyun unsigned int phy_con2; 333*4882a593Smuzhiyun unsigned int phy_con3; 334*4882a593Smuzhiyun unsigned int phy_con4; 335*4882a593Smuzhiyun unsigned char res1[4]; 336*4882a593Smuzhiyun unsigned int phy_con6; 337*4882a593Smuzhiyun unsigned char res2[4]; 338*4882a593Smuzhiyun unsigned int phy_con8; 339*4882a593Smuzhiyun unsigned int phy_con9; 340*4882a593Smuzhiyun unsigned int phy_con10; 341*4882a593Smuzhiyun unsigned char res3[4]; 342*4882a593Smuzhiyun unsigned int phy_con12; 343*4882a593Smuzhiyun unsigned int phy_con13; 344*4882a593Smuzhiyun unsigned int phy_con14; 345*4882a593Smuzhiyun unsigned int phy_con15; 346*4882a593Smuzhiyun unsigned int phy_con16; 347*4882a593Smuzhiyun unsigned char res4[4]; 348*4882a593Smuzhiyun unsigned int phy_con17; 349*4882a593Smuzhiyun unsigned int phy_con18; 350*4882a593Smuzhiyun unsigned int phy_con19; 351*4882a593Smuzhiyun unsigned int phy_con20; 352*4882a593Smuzhiyun unsigned int phy_con21; 353*4882a593Smuzhiyun unsigned int phy_con22; 354*4882a593Smuzhiyun unsigned int phy_con23; 355*4882a593Smuzhiyun unsigned int phy_con24; 356*4882a593Smuzhiyun unsigned int phy_con25; 357*4882a593Smuzhiyun unsigned int phy_con26; 358*4882a593Smuzhiyun unsigned int phy_con27; 359*4882a593Smuzhiyun unsigned int phy_con28; 360*4882a593Smuzhiyun unsigned int phy_con29; 361*4882a593Smuzhiyun unsigned int phy_con30; 362*4882a593Smuzhiyun unsigned int phy_con31; 363*4882a593Smuzhiyun unsigned int phy_con32; 364*4882a593Smuzhiyun unsigned int phy_con33; 365*4882a593Smuzhiyun unsigned int phy_con34; 366*4882a593Smuzhiyun unsigned int phy_con35; 367*4882a593Smuzhiyun unsigned int phy_con36; 368*4882a593Smuzhiyun unsigned int phy_con37; 369*4882a593Smuzhiyun unsigned int phy_con38; 370*4882a593Smuzhiyun unsigned int phy_con39; 371*4882a593Smuzhiyun unsigned int phy_con40; 372*4882a593Smuzhiyun unsigned int phy_con41; 373*4882a593Smuzhiyun unsigned int phy_con42; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun struct exynos5420_phy_control { 377*4882a593Smuzhiyun unsigned int phy_con0; 378*4882a593Smuzhiyun unsigned int phy_con1; 379*4882a593Smuzhiyun unsigned int phy_con2; 380*4882a593Smuzhiyun unsigned int phy_con3; 381*4882a593Smuzhiyun unsigned int phy_con4; 382*4882a593Smuzhiyun unsigned int phy_con5; 383*4882a593Smuzhiyun unsigned int phy_con6; 384*4882a593Smuzhiyun unsigned char res2[0x4]; 385*4882a593Smuzhiyun unsigned int phy_con8; 386*4882a593Smuzhiyun unsigned char res5[0x4]; 387*4882a593Smuzhiyun unsigned int phy_con10; 388*4882a593Smuzhiyun unsigned int phy_con11; 389*4882a593Smuzhiyun unsigned int phy_con12; 390*4882a593Smuzhiyun unsigned int phy_con13; 391*4882a593Smuzhiyun unsigned int phy_con14; 392*4882a593Smuzhiyun unsigned int phy_con15; 393*4882a593Smuzhiyun unsigned int phy_con16; 394*4882a593Smuzhiyun unsigned char res4[0x4]; 395*4882a593Smuzhiyun unsigned int phy_con17; 396*4882a593Smuzhiyun unsigned int phy_con18; 397*4882a593Smuzhiyun unsigned int phy_con19; 398*4882a593Smuzhiyun unsigned int phy_con20; 399*4882a593Smuzhiyun unsigned int phy_con21; 400*4882a593Smuzhiyun unsigned int phy_con22; 401*4882a593Smuzhiyun unsigned int phy_con23; 402*4882a593Smuzhiyun unsigned int phy_con24; 403*4882a593Smuzhiyun unsigned int phy_con25; 404*4882a593Smuzhiyun unsigned int phy_con26; 405*4882a593Smuzhiyun unsigned int phy_con27; 406*4882a593Smuzhiyun unsigned int phy_con28; 407*4882a593Smuzhiyun unsigned int phy_con29; 408*4882a593Smuzhiyun unsigned int phy_con30; 409*4882a593Smuzhiyun unsigned int phy_con31; 410*4882a593Smuzhiyun unsigned int phy_con32; 411*4882a593Smuzhiyun unsigned int phy_con33; 412*4882a593Smuzhiyun unsigned int phy_con34; 413*4882a593Smuzhiyun unsigned char res6[0x8]; 414*4882a593Smuzhiyun unsigned int phy_con37; 415*4882a593Smuzhiyun unsigned char res7[0x4]; 416*4882a593Smuzhiyun unsigned int phy_con39; 417*4882a593Smuzhiyun unsigned int phy_con40; 418*4882a593Smuzhiyun unsigned int phy_con41; 419*4882a593Smuzhiyun unsigned int phy_con42; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun struct exynos5420_tzasc { 423*4882a593Smuzhiyun unsigned char res1[0xf00]; 424*4882a593Smuzhiyun unsigned int membaseconfig0; 425*4882a593Smuzhiyun unsigned int membaseconfig1; 426*4882a593Smuzhiyun unsigned char res2[0x8]; 427*4882a593Smuzhiyun unsigned int memconfig0; 428*4882a593Smuzhiyun unsigned int memconfig1; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun enum ddr_mode { 432*4882a593Smuzhiyun DDR_MODE_DDR2, 433*4882a593Smuzhiyun DDR_MODE_DDR3, 434*4882a593Smuzhiyun DDR_MODE_LPDDR2, 435*4882a593Smuzhiyun DDR_MODE_LPDDR3, 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun DDR_MODE_COUNT, 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun enum mem_manuf { 441*4882a593Smuzhiyun MEM_MANUF_AUTODETECT, 442*4882a593Smuzhiyun MEM_MANUF_ELPIDA, 443*4882a593Smuzhiyun MEM_MANUF_SAMSUNG, 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun MEM_MANUF_COUNT, 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun /* CONCONTROL register fields */ 449*4882a593Smuzhiyun #define CONCONTROL_DFI_INIT_START_SHIFT 28 450*4882a593Smuzhiyun #define CONCONTROL_RD_FETCH_SHIFT 12 451*4882a593Smuzhiyun #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) 452*4882a593Smuzhiyun #define CONCONTROL_AREF_EN_SHIFT 5 453*4882a593Smuzhiyun #define CONCONTROL_UPDATE_MODE (1 << 3) 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun /* PRECHCONFIG register field */ 456*4882a593Smuzhiyun #define PRECHCONFIG_TP_CNT_SHIFT 24 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /* PWRDNCONFIG register field */ 459*4882a593Smuzhiyun #define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 460*4882a593Smuzhiyun #define PWRDNCONFIG_DSREF_CYC_SHIFT 16 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun /* PHY_CON0 register fields */ 463*4882a593Smuzhiyun #define PHY_CON0_T_WRRDCMD_SHIFT 17 464*4882a593Smuzhiyun #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) 465*4882a593Smuzhiyun #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 466*4882a593Smuzhiyun #define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* PHY_CON1 register fields */ 469*4882a593Smuzhiyun #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun /* PHY_CON4 rgister fields */ 472*4882a593Smuzhiyun #define PHY_CON10_CTRL_OFFSETR3 (1 << 24) 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* PHY_CON12 register fields */ 475*4882a593Smuzhiyun #define PHY_CON12_CTRL_START_POINT_SHIFT 24 476*4882a593Smuzhiyun #define PHY_CON12_CTRL_INC_SHIFT 16 477*4882a593Smuzhiyun #define PHY_CON12_CTRL_FORCE_SHIFT 8 478*4882a593Smuzhiyun #define PHY_CON12_CTRL_START_SHIFT 6 479*4882a593Smuzhiyun #define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) 480*4882a593Smuzhiyun #define PHY_CON12_CTRL_DLL_ON_SHIFT 5 481*4882a593Smuzhiyun #define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) 482*4882a593Smuzhiyun #define PHY_CON12_CTRL_REF_SHIFT 1 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /* PHY_CON16 register fields */ 485*4882a593Smuzhiyun #define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 486*4882a593Smuzhiyun #define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun #define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 489*4882a593Smuzhiyun #define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun #define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun /* PHY_CON42 register fields */ 494*4882a593Smuzhiyun #define PHY_CON42_CTRL_BSTLEN_SHIFT 8 495*4882a593Smuzhiyun #define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #define PHY_CON42_CTRL_RDLAT_SHIFT 0 498*4882a593Smuzhiyun #define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun #endif 501*4882a593Smuzhiyun #endif 502