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Searched refs:crc_pll (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dclock.c82 return &clkrst->crc_pll[clkid]; in get_pll()
794 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
800 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
805 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
811 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c945 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
949 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
954 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
960 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
1016 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1024 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
1030 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c666 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
699 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
703 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
710 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c846 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
879 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
883 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
890 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c203 writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); in wb_start()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclk_rst.h78 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ member