Searched refs:UCR1_RRDYEN (Results 1 – 3 of 3) sorted by relevance
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro436 ucr1 |= UCR1_RRDYEN; in imx_uart_start_rx()518 ucr1 &= ~UCR1_RRDYEN; in imx_uart_stop_rx()970 if ((ucr1 & UCR1_RRDYEN) == 0) in imx_uart_int()1463 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()1515 ucr1 |= UCR1_RRDYEN; in imx_uart_startup()1576 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); in imx_uart_shutdown()1883 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()1892 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()2029 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()[all …]
29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro
531 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro