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Searched refs:SDRAM_CS_SIZE (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c511 cs_num = (src / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
514 channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
518 cs_num = (dst / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
522 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
524 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
H A Dddr3_init.c174 reg |= (SDRAM_CS_SIZE & 0xFFFF0000); in ddr3_restore_and_set_final_windows()
178 reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000); in ddr3_restore_and_set_final_windows()
249 reg |= (SDRAM_CS_SIZE & 0xFFFF0000); in ddr3_save_and_set_training_windows()
253 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; in ddr3_save_and_set_training_windows()
H A Dddr3_axp.h24 #define SDRAM_CS_SIZE 0xFFFFFFF macro
26 #define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) macro
H A Dddr3_dqs.c338 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1); in ddr3_find_adll_limits()
980 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS + in ddr3_special_pattern_i_search()
1136 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS; in ddr3_special_pattern_ii_search()
1344 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
1359 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
H A Dddr3_read_leveling.c457 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_rl_mode()
811 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_pbs.c1569 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
1579 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
H A Dddr3_write_leveling.c265 tmp_count * (SDRAM_CS_SIZE + 1) + in ddr3_wl_supplement()
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c262 reg |= (SDRAM_CS_SIZE & 0xffff0000); in ddr3_save_and_set_training_windows()
266 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & in ddr3_save_and_set_training_windows()
H A Dddr3_hws_hw_training_def.h20 #define SDRAM_CS_SIZE 0xfffffff macro
H A Dddr3_training_leveling.c1483 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, in ddr3_tip_xsb_compare_test()
1491 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern)); in ddr3_tip_xsb_compare_test()