Home
last modified time | relevance | path

Searched refs:REGISTER_PART_ANALOG (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dinno_video_combo_phy.c317 REGISTER_PART_ANALOG, enumerator
401 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
403 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
407 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
409 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
420 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
422 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
424 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c253 REGISTER_PART_ANALOG, enumerator
423 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
[all …]
H A Dphy-rockchip-inno-video-combo-phy.c220 REGISTER_PART_ANALOG, enumerator
318 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_mipi_mode_enable()
320 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_mipi_mode_enable()
322 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_video_phy_mipi_mode_enable()
325 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
329 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
332 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_video_phy_mipi_mode_enable()
455 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_video_phy_lvds_mode_enable()
463 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_lvds_mode_enable()
[all …]
H A Dphy-rockchip-inno-mipi-dphy.c238 REGISTER_PART_ANALOG, enumerator
286 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
289 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
301 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_power_work_enable()
307 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_power_work_disable()
313 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_bandgap_power_enable()
319 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_bandgap_power_disable()
343 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val); in inno_mipi_dphy_lane_enable()
348 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); in inno_mipi_dphy_lane_disable()
353 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_pll_enable()
[all …]