| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/ |
| H A D | rk628_hdmirx.c | 27 #define REG(x) ((x) + 0x30000) macro
28 #define HDMI_RX_HDMI_SETUP_CTRL REG(0x0000)
31 #define HDMI_RX_HDMI_OVR_CTRL REG(0x0004)
32 #define HDMI_RX_HDMI_TIMER_CTRL REG(0x0008)
33 #define HDMI_RX_HDMI_RES_OVR REG(0x0010)
34 #define HDMI_RX_HDMI_RES_STS REG(0x0014)
35 #define HDMI_RX_HDMI_PLL_CTRL REG(0x0018)
36 #define HDMI_RX_HDMI_PLL_FRQSET1 REG(0x001c)
37 #define HDMI_RX_HDMI_PLL_FRQSET2 REG(0x0020)
38 #define HDMI_RX_HDMI_PLL_PAR1 REG(0x0024)
[all …]
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| H A D | rk628_combrxphy.c | 28 #define REG(x) ((x) + 0x10000) macro
29 #define COMBRXPHY_MAX_REGISTER REG(0x6790)
144 regmap_read(combrxphy->regmap, REG(0x6740 + i * 4), &data[i]); in rk628_combrxphy_get_data_of_round()
160 regmap_read(combrxphy->regmap, REG(0x661c), &val); in rk628_combrxphy_set_dc_gain()
164 regmap_write(combrxphy->regmap, REG(0x661c), val); in rk628_combrxphy_set_dc_gain()
179 regmap_read(combrxphy->regmap, REG(0x6618), &val); in rk628_combrxphy_set_sample_edge_round()
182 regmap_write(combrxphy->regmap, REG(0x6618), val); in rk628_combrxphy_set_sample_edge_round()
189 regmap_read(combrxphy->regmap, REG(0x66f0), &val); in rk628_combrxphy_start_sample_edge()
191 regmap_write(combrxphy->regmap, REG(0x66f0), val); in rk628_combrxphy_start_sample_edge()
192 regmap_read(combrxphy->regmap, REG(0x66f0), &val); in rk628_combrxphy_start_sample_edge()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/mscc/ |
| H A D | ocelot_vsc7514.c | 24 REG(ANA_ADVLEARN, 0x009000),
25 REG(ANA_VLANMASK, 0x009004),
26 REG(ANA_PORT_B_DOMAIN, 0x009008),
27 REG(ANA_ANAGEFIL, 0x00900c),
28 REG(ANA_ANEVENTS, 0x009010),
29 REG(ANA_STORMLIMIT_BURST, 0x009014),
30 REG(ANA_STORMLIMIT_CFG, 0x009018),
31 REG(ANA_ISOLATED_PORTS, 0x009028),
32 REG(ANA_COMMUNITY_PORTS, 0x00902c),
33 REG(ANA_AUTOAGE, 0x009030),
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/dsa/ocelot/ |
| H A D | felix_vsc9959.c | 22 REG(ANA_ADVLEARN, 0x0089a0),
23 REG(ANA_VLANMASK, 0x0089a4),
25 REG(ANA_ANAGEFIL, 0x0089ac),
26 REG(ANA_ANEVENTS, 0x0089b0),
27 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
28 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
29 REG(ANA_ISOLATED_PORTS, 0x0089c8),
30 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
31 REG(ANA_AUTOAGE, 0x0089d0),
32 REG(ANA_MACTOPTIONS, 0x0089d4),
[all …]
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| H A D | seville_vsc9953.c | 23 REG(ANA_ADVLEARN, 0x00b500),
24 REG(ANA_VLANMASK, 0x00b504),
26 REG(ANA_ANAGEFIL, 0x00b50c),
27 REG(ANA_ANEVENTS, 0x00b510),
28 REG(ANA_STORMLIMIT_BURST, 0x00b514),
29 REG(ANA_STORMLIMIT_CFG, 0x00b518),
30 REG(ANA_ISOLATED_PORTS, 0x00b528),
31 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
32 REG(ANA_AUTOAGE, 0x00b530),
33 REG(ANA_MACTOPTIONS, 0x00b534),
[all …]
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| /OK3568_Linux_fs/u-boot/board/imx31_phycore/ |
| H A D | lowlevel_init.S | 10 .macro REG reg, val macro
33 REG IPU_CONF, IPU_CONF_DI_EN
34 REG CCM_CCMR, 0x074B0BF5
38 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
39 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
41 …REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_…
43 REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
45 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
47 REG 0x43FAC26C, 0 /* SDCLK */
48 REG 0x43FAC270, 0 /* CAS */
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/csky/util/ |
| H A D | unwind-libdw.c | 15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
23 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(REGS4); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/s390/util/ |
| H A D | unwind-libdw.c | 15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
24 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
25 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
26 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
27 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
28 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
29 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
30 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
31 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
32 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/arm64/util/ |
| H A D | unwind-libdw.c | 13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(X0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(X1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(X2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(X3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(X4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(X5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(X6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(X7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(X8); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/riscv/util/ |
| H A D | unwind-libdw.c | 15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[1] = REG(RA); in libdw__arch_set_initial_registers()
23 dwarf_regs[2] = REG(SP); in libdw__arch_set_initial_registers()
24 dwarf_regs[3] = REG(GP); in libdw__arch_set_initial_registers()
25 dwarf_regs[4] = REG(TP); in libdw__arch_set_initial_registers()
26 dwarf_regs[5] = REG(T0); in libdw__arch_set_initial_registers()
27 dwarf_regs[6] = REG(T1); in libdw__arch_set_initial_registers()
28 dwarf_regs[7] = REG(T2); in libdw__arch_set_initial_registers()
29 dwarf_regs[8] = REG(S0); in libdw__arch_set_initial_registers()
30 dwarf_regs[9] = REG(S1); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/powerpc/util/ |
| H A D | unwind-libdw.c | 22 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
28 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
29 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
30 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
31 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
32 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
33 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
34 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
35 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
36 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/apple/ |
| H A D | mace.h | 9 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
14 REG(xmtfc); /* transmit frame control */
15 REG(xmtfs); /* transmit frame status */
16 REG(xmtrc); /* transmit retry count */
17 REG(rcvfc); /* receive frame control */
18 REG(rcvfs); /* receive frame status (4 bytes) */
19 REG(fifofc); /* FIFO frame count */
20 REG(ir); /* interrupt register */
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/x86/util/ |
| H A D | unwind-libdw.c | 14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
21 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
22 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
23 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
24 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
25 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
26 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
27 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
28 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
29 dwarf_regs[8] = REG(IP); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/regulator/ |
| H A D | rn5t618-regulator.c | 25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/tidss/ |
| H A D | tidss_dispc_regs.h | 55 #define REG(r) (dispc_common_regmap[r ## _OFF]) macro
57 #define DSS_REVISION REG(DSS_REVISION)
58 #define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
59 #define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
60 #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
61 #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW)
62 #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
63 #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET)
64 #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR)
65 #define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4)
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/i2c/ |
| H A D | davinci_i2c.c | 35 REG(&(i2c_base->i2c_con)) = 0;\
44 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
47 stat = REG(&(i2c_base->i2c_stat)); in _wait_for_bus()
49 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
53 REG(&(i2c_base->i2c_stat)) = stat; in _wait_for_bus()
57 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
67 stat = REG(&(i2c_base->i2c_stat)); in _poll_i2c_irq()
72 REG(&(i2c_base->i2c_stat)) = 0xffff; in _poll_i2c_irq()
79 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) in _flush_rx()
82 REG(&(i2c_base->i2c_drr)); in _flush_rx()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_translate_dce120.c | 51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_translate_dcn10.c | 51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
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| /OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/nx-gzip/include/ |
| H A D | nxu.h | 428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \ argument
429 & REG##_mask)
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \ argument
431 & REG##_mask)
432 #define get32(ST, REG) (be32toh(ST.REG)) argument
433 #define getp32(ST, REG) (be32toh((ST)->REG)) argument
434 #define get64(ST, REG) (be64toh(ST.REG)) argument
435 #define getp64(ST, REG) (be64toh((ST)->REG)) argument
437 #define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \ argument
438 << (31-REG##_offset)))
[all …]
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| /OK3568_Linux_fs/kernel/tools/perf/arch/arm/util/ |
| H A D | unwind-libdw.c | 13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
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| /OK3568_Linux_fs/kernel/arch/sparc/include/asm/ |
| H A D | trap_block.h | 120 #define __GET_CPUID(REG) \ argument
122 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
123 srlx REG, 17, REG; \
124 and REG, 0x1f, REG; \
130 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
131 srlx REG, 17, REG; \
132 and REG, 0x3ff, REG; \
135 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
136 srlx REG, 17, REG; \
137 and REG, 0x1f, REG; \
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dpp_cm.c | 42 #define REG(reg)\ macro
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
220 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
221 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); in dpp1_cm_program_color_matrix()
225 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in dpp1_cm_program_color_matrix()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dwb_cm.c | 36 #define REG(reg)\ macro
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); in dwb3_program_ogam_luta_settings()
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); in dwb3_program_ogam_luta_settings()
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); in dwb3_program_ogam_luta_settings()
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); in dwb3_program_ogam_luta_settings()
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); in dwb3_program_ogam_luta_settings()
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); in dwb3_program_ogam_luta_settings()
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); in dwb3_program_ogam_luta_settings()
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); in dwb3_program_ogam_luta_settings()
97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R); in dwb3_program_ogam_luta_settings()
[all …]
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| H A D | dcn30_dpp_cm.c | 33 #define REG(reg)\ macro
247 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); in dpp3_program_gamcor_lut()
248 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G); in dpp3_program_gamcor_lut()
249 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R); in dpp3_program_gamcor_lut()
250 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B); in dpp3_program_gamcor_lut()
251 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G); in dpp3_program_gamcor_lut()
252 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R); in dpp3_program_gamcor_lut()
253 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B); in dpp3_program_gamcor_lut()
254 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B); in dpp3_program_gamcor_lut()
255 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G); in dpp3_program_gamcor_lut()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_translate_dcn20.c | 54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
157 case REG(DC_GPIO_DDC2_A): in offset_to_id()
160 case REG(DC_GPIO_DDC3_A): in offset_to_id()
163 case REG(DC_GPIO_DDC4_A): in offset_to_id()
166 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
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