Home
last modified time | relevance | path

Searched refs:PLLE_SS_CNTL_SSCINC (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c623 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
739 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
740 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c652 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
785 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
786 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c935 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
1017 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
1021 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1121 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
1221 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
1222 value |= PLLE_SS_CNTL_SSCINC(1); in tegra_plle_enable()