Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance
| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 933 #define PLLE_SS_CNTL 0x68 macro
989 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
992 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1012 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1024 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1029 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1033 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 621 #define PLLE_SS_CNTL 0x68 macro
711 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
714 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
735 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
748 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 650 #define PLLE_SS_CNTL 0x68 macro
757 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
760 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
781 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
794 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 1119 #define PLLE_SS_CNTL 0x68 macro
1220 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1231 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1237 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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