Searched refs:PIPESTAT (Results 1 – 6 of 6) sorted by relevance
93 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()114 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
19060 PIPESTAT(i)); in intel_display_capture_error_state()
470 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()563 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()603 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
493 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()516 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()1295 I915_WRITE(PIPESTAT(pipe), in i9xx_pipestat_irq_reset()1348 reg = PIPESTAT(pipe); in i9xx_pipestat_irq_ack()
6012 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) macro
2045 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()2046 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()2047 MMIO_D(PIPESTAT(PIPE_C), D_ALL); in init_generic_mmio_info()2048 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); in init_generic_mmio_info()