Searched refs:PHYS_SDRAM_0 (Results 1 – 7 of 7) sorted by relevance
207 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro210 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro212 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ macro217 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */234 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0251 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0252 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
112 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro115 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */122 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0134 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0135 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
112 #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE macro
34 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()41 unsigned long sdram_base = PHYS_SDRAM_0; in dram_init()59 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
30 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()36 unsigned long sdram_base = PHYS_SDRAM_0; in dram_init()51 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
180 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); in board_init()240 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); in dram_init()
690 return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); in dramc_init_helper()