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Searched refs:IMX6QDL_CLK_PLL5_VIDEO_DIV (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6q-logicpd.dts65 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
66 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
H A Dimx6q-bx50v3.dtsi403 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
404 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
H A Dimx6dl-prtvt7.dts218 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
H A Dimx6qdl-zii-rdu2.dtsi222 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
223 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx6q.c146 case IMX6QDL_CLK_PLL5_VIDEO_DIV: in ldb_di_sel_by_clock_id()
599 …hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post… in imx6q_clocks_init()
921 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
922 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
923 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
924 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dimx6qdl-clock.h208 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dimx6qdl-clock.h205 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 macro