1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2016 Protonic Holland 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx6dl.dtsi" 8*4882a593Smuzhiyun#include "imx6qdl-prti6q.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/leds/common.h> 11*4882a593Smuzhiyun#include <dt-bindings/sound/fsl-imx-audmux.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Protonic VT7"; 15*4882a593Smuzhiyun compatible = "prt,prtvt7", "fsl,imx6dl"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@10000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun reg = <0x10000000 0x20000000>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun backlight_lcd: backlight-lcd { 23*4882a593Smuzhiyun compatible = "pwm-backlight"; 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_backlight>; 26*4882a593Smuzhiyun pwms = <&pwm1 0 500000>; 27*4882a593Smuzhiyun brightness-levels = <0 20 81 248 1000>; 28*4882a593Smuzhiyun default-brightness-level = <20>; 29*4882a593Smuzhiyun num-interpolated-steps = <21>; 30*4882a593Smuzhiyun power-supply = <®_bl_12v0>; 31*4882a593Smuzhiyun enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun keys { 35*4882a593Smuzhiyun compatible = "gpio-keys"; 36*4882a593Smuzhiyun autorepeat; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun esc { 39*4882a593Smuzhiyun label = "GPIO Key ESC"; 40*4882a593Smuzhiyun linux,code = <KEY_ESC>; 41*4882a593Smuzhiyun gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun up { 45*4882a593Smuzhiyun label = "GPIO Key UP"; 46*4882a593Smuzhiyun linux,code = <KEY_UP>; 47*4882a593Smuzhiyun gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun down { 51*4882a593Smuzhiyun label = "GPIO Key DOWN"; 52*4882a593Smuzhiyun linux,code = <KEY_DOWN>; 53*4882a593Smuzhiyun gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun enter { 57*4882a593Smuzhiyun label = "GPIO Key Enter"; 58*4882a593Smuzhiyun linux,code = <KEY_ENTER>; 59*4882a593Smuzhiyun gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun cycle { 63*4882a593Smuzhiyun label = "GPIO Key CYCLE"; 64*4882a593Smuzhiyun linux,code = <KEY_CYCLEWINDOWS>; 65*4882a593Smuzhiyun gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun f1 { 69*4882a593Smuzhiyun label = "GPIO Key F1"; 70*4882a593Smuzhiyun linux,code = <KEY_F1>; 71*4882a593Smuzhiyun gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun f2 { 75*4882a593Smuzhiyun label = "GPIO Key F2"; 76*4882a593Smuzhiyun linux,code = <KEY_F2>; 77*4882a593Smuzhiyun gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun f3 { 81*4882a593Smuzhiyun label = "GPIO Key F3"; 82*4882a593Smuzhiyun linux,code = <KEY_F3>; 83*4882a593Smuzhiyun gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun f4 { 87*4882a593Smuzhiyun label = "GPIO Key F4"; 88*4882a593Smuzhiyun linux,code = <KEY_F4>; 89*4882a593Smuzhiyun gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun f5 { 93*4882a593Smuzhiyun label = "GPIO Key F5"; 94*4882a593Smuzhiyun linux,code = <KEY_F5>; 95*4882a593Smuzhiyun gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun f6 { 99*4882a593Smuzhiyun label = "GPIO Key F6"; 100*4882a593Smuzhiyun linux,code = <KEY_F6>; 101*4882a593Smuzhiyun gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun f7 { 105*4882a593Smuzhiyun label = "GPIO Key F7"; 106*4882a593Smuzhiyun linux,code = <KEY_F7>; 107*4882a593Smuzhiyun gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun f8 { 111*4882a593Smuzhiyun label = "GPIO Key F8"; 112*4882a593Smuzhiyun linux,code = <KEY_F8>; 113*4882a593Smuzhiyun gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun f9 { 117*4882a593Smuzhiyun label = "GPIO Key F9"; 118*4882a593Smuzhiyun linux,code = <KEY_F9>; 119*4882a593Smuzhiyun gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun f10 { 123*4882a593Smuzhiyun label = "GPIO Key F10"; 124*4882a593Smuzhiyun linux,code = <KEY_F10>; 125*4882a593Smuzhiyun gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun leds { 130*4882a593Smuzhiyun compatible = "gpio-leds"; 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_leds>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun led-debug0 { 135*4882a593Smuzhiyun function = LED_FUNCTION_STATUS; 136*4882a593Smuzhiyun gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 137*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun reg_bl_12v0: regulator-bl-12v0 { 142*4882a593Smuzhiyun compatible = "regulator-fixed"; 143*4882a593Smuzhiyun pinctrl-names = "default"; 144*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_reg_bl_12v0>; 145*4882a593Smuzhiyun regulator-name = "bl-12v0"; 146*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 147*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 148*4882a593Smuzhiyun gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 149*4882a593Smuzhiyun enable-active-high; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun reg_1v8: regulator-1v8 { 153*4882a593Smuzhiyun compatible = "regulator-fixed"; 154*4882a593Smuzhiyun regulator-name = "1v8"; 155*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 156*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun sound { 160*4882a593Smuzhiyun compatible = "simple-audio-card"; 161*4882a593Smuzhiyun simple-audio-card,name = "prti6q-sgtl5000"; 162*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 163*4882a593Smuzhiyun simple-audio-card,widgets = 164*4882a593Smuzhiyun "Microphone", "Microphone Jack", 165*4882a593Smuzhiyun "Line", "Line In Jack", 166*4882a593Smuzhiyun "Headphone", "Headphone Jack", 167*4882a593Smuzhiyun "Speaker", "External Speaker"; 168*4882a593Smuzhiyun simple-audio-card,routing = 169*4882a593Smuzhiyun "MIC_IN", "Microphone Jack", 170*4882a593Smuzhiyun "LINE_IN", "Line In Jack", 171*4882a593Smuzhiyun "Headphone Jack", "HP_OUT", 172*4882a593Smuzhiyun "External Speaker", "LINE_OUT"; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun simple-audio-card,cpu { 175*4882a593Smuzhiyun sound-dai = <&ssi1>; 176*4882a593Smuzhiyun system-clock-frequency = <0>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun simple-audio-card,codec { 180*4882a593Smuzhiyun sound-dai = <&sgtl5000>; 181*4882a593Smuzhiyun bitclock-master; 182*4882a593Smuzhiyun frame-master; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&audmux { 188*4882a593Smuzhiyun pinctrl-names = "default"; 189*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 190*4882a593Smuzhiyun status = "okay"; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun mux-ssi1 { 193*4882a593Smuzhiyun fsl,audmux-port = <0>; 194*4882a593Smuzhiyun fsl,port-config = < 195*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_SYN 0 196*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 197*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 198*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSDIR 0 199*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 200*4882a593Smuzhiyun >; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun mux-pins3 { 204*4882a593Smuzhiyun fsl,audmux-port = <2>; 205*4882a593Smuzhiyun fsl,port-config = < 206*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 207*4882a593Smuzhiyun 0 IMX_AUDMUX_V2_PDCR_TXRXEN 208*4882a593Smuzhiyun >; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&can1 { 213*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&clks { 217*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; 218*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; 219*4882a593Smuzhiyun}; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun&ecspi2 { 222*4882a593Smuzhiyun cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 223*4882a593Smuzhiyun pinctrl-names = "default"; 224*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi2>; 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&i2c1 { 229*4882a593Smuzhiyun sgtl5000: audio-codec@a { 230*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 231*4882a593Smuzhiyun reg = <0xa>; 232*4882a593Smuzhiyun pinctrl-names = "default"; 233*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_codec>; 234*4882a593Smuzhiyun #sound-dai-cells = <0>; 235*4882a593Smuzhiyun clocks = <&clks 201>; 236*4882a593Smuzhiyun VDDA-supply = <®_3v3>; 237*4882a593Smuzhiyun VDDIO-supply = <®_3v3>; 238*4882a593Smuzhiyun VDDD-supply = <®_1v8>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&i2c3 { 243*4882a593Smuzhiyun rtc@51 { 244*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 245*4882a593Smuzhiyun reg = <0x51>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun gpio_pca: gpio@74 { 249*4882a593Smuzhiyun compatible = "nxp,pca9539"; 250*4882a593Smuzhiyun reg = <0x74>; 251*4882a593Smuzhiyun interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; 252*4882a593Smuzhiyun #gpio-cells = <2>; 253*4882a593Smuzhiyun gpio-controller; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&ipu1 { 258*4882a593Smuzhiyun pinctrl-names = "default"; 259*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu1_csi0>; 260*4882a593Smuzhiyun status = "okay"; 261*4882a593Smuzhiyun}; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun&pwm1 { 264*4882a593Smuzhiyun #pwm-cells = <2>; 265*4882a593Smuzhiyun pinctrl-names = "default"; 266*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 267*4882a593Smuzhiyun status = "okay"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&snvs_poweroff { 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&snvs_pwrkey { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&ssi1 { 279*4882a593Smuzhiyun #sound-dai-cells = <0>; 280*4882a593Smuzhiyun fsl,mode = "ac97-slave"; 281*4882a593Smuzhiyun status = "okay"; 282*4882a593Smuzhiyun}; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun&usbh1 { 285*4882a593Smuzhiyun status = "disabled"; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&vpu { 289*4882a593Smuzhiyun status = "disabled"; 290*4882a593Smuzhiyun}; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun&iomuxc { 293*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 294*4882a593Smuzhiyun fsl,pins = < 295*4882a593Smuzhiyun MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 296*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 297*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 298*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 299*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 300*4882a593Smuzhiyun >; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun pinctrl_backlight: backlightgrp { 304*4882a593Smuzhiyun fsl,pins = < 305*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 306*4882a593Smuzhiyun >; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun pinctrl_can1phy: can1phy { 310*4882a593Smuzhiyun fsl,pins = < 311*4882a593Smuzhiyun /* CAN1_SR */ 312*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 313*4882a593Smuzhiyun /* CAN1_TERM */ 314*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 315*4882a593Smuzhiyun >; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun pinctrl_codec: codecgrp { 319*4882a593Smuzhiyun fsl,pins = < 320*4882a593Smuzhiyun /* AUDIO_nRESET */ 321*4882a593Smuzhiyun MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 322*4882a593Smuzhiyun >; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun pinctrl_ecspi2: ecspi2grp { 326*4882a593Smuzhiyun fsl,pins = < 327*4882a593Smuzhiyun MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 328*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 329*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 330*4882a593Smuzhiyun MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 331*4882a593Smuzhiyun >; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun pinctrl_ipu1_csi0: ipu1csi0grp { 335*4882a593Smuzhiyun fsl,pins = < 336*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 337*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 338*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 339*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 340*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 341*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 342*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 343*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 344*4882a593Smuzhiyun MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 345*4882a593Smuzhiyun /* ITU656_nRESET */ 346*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 347*4882a593Smuzhiyun /* ITU656_nPDN */ 348*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 349*4882a593Smuzhiyun >; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun pinctrl_ipu1_disp: ipudisp1grp { 353*4882a593Smuzhiyun fsl,pins = < 354*4882a593Smuzhiyun MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 355*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 358*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 359*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 360*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 361*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 362*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 363*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 364*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 367*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 368*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 369*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 370*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 371*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 372*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 373*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 376*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 377*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 378*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 379*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 380*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 381*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 382*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 383*4882a593Smuzhiyun >; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun pinctrl_leds: ledsgrp { 387*4882a593Smuzhiyun fsl,pins = < 388*4882a593Smuzhiyun MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 389*4882a593Smuzhiyun >; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 393*4882a593Smuzhiyun fsl,pins = < 394*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 395*4882a593Smuzhiyun >; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun pinctrl_reg_bl_12v0: 12blgrp { 399*4882a593Smuzhiyun fsl,pins = < 400*4882a593Smuzhiyun MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 401*4882a593Smuzhiyun >; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun pinctrl_tsc: tscgrp { 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun fsl,pins = < 407*4882a593Smuzhiyun MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 408*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 409*4882a593Smuzhiyun >; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun}; 412