Searched refs:GPIO4_IOC_BASE (Results 1 – 3 of 3) sorted by relevance
119 #define GPIO4_IOC_BASE 0xFF568000 macro159 #define UART0_RX_M2_ADDR (GPIO4_IOC_BASE)163 #define UART0_TX_M2_ADDR (GPIO4_IOC_BASE)187 #define UART1_RX_M2_ADDR (GPIO4_IOC_BASE + 0x4)191 #define UART1_TX_M2_ADDR (GPIO4_IOC_BASE + 0x4)276 #define UART5_TX_M2_ADDR (GPIO4_IOC_BASE + 0x54)433 if ((readl(GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L) & 0x70) == 0x20) in arch_cpu_init()434 writel(0x3f000700, GPIO4_IOC_BASE + GPIO4_IOC_GPIO4B_DS0); in arch_cpu_init()486 writel(0x0f000700, GPIO4_IOC_BASE + 0x0030); in arch_cpu_init()487 writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L); in arch_cpu_init()[all …]
79 #define GPIO4_IOC_BASE 0xFF550000 macro92 #define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)96 #define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)120 #define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)124 #define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)149 #define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)153 #define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)158 #define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)162 #define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
142 #define GPIO4_IOC_BASE 0xFF070000 macro176 #define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x64)180 #define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)205 #define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)209 #define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)271 #define UART6_RX_M1_ADDR (GPIO4_IOC_BASE + 0x68)275 #define UART6_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)319 #define UART9_RX_M0_ADDR (GPIO4_IOC_BASE + 0x68)323 #define UART9_TX_M0_ADDR (GPIO4_IOC_BASE + 0x68)