1 /*
2 * Copyright (c) 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <asm/io.h>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/grf_rk3528.h>
12 #include <asm/arch/ioc_rk3528.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #define FIREWALL_DDR_BASE 0xff2e0000
17 #define FW_DDR_MST1_REG 0x44
18 #define FW_DDR_MST6_REG 0x58
19 #define FW_DDR_MST7_REG 0x5c
20 #define FW_DDR_MST11_REG 0x6c
21 #define FW_DDR_MST14_REG 0x78
22 #define FW_DDR_MST16_REG 0x80
23 #define FW_DDR_MST_REG 0xf0
24
25 #define VENC_GRF_BASE 0xff320000
26 #define VENC_GRF_CON1 0x4
27
28 #define VPU_GRF_BASE 0xff340000
29 #define VPU_GRF_CON4 0x14
30
31 #define PMU_SGRF_BASE 0xff440000
32 #define PMU_SGRF_SOC_CON4 0x10
33 #define PMU_SGRF_SOC_CON5 0x14
34 #define PMU_SGRF_SOC_CON6 0x18
35 #define PMU_SGRF_SOC_CON8 0x20
36 #define PMU_SGRF_SOC_CON11 0x2c
37
38 #define PMU_CRU_BASE 0xff4b0000
39 #define PMU_CRU_GATE_CON00 0x800
40 #define PMU_CRU_SOFTRST_CON00 0xa00
41
42 #define GPIO1C_IOMUX_SEL_H 0x034
43 #define GPIO1D_IOMUX_SEL_L 0x038
44 #define GPIO1D_IOMUX_SEL_H 0x03c
45
46 #define CPU_PRIORITY_REG 0xff210008
47 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
48
49 #ifdef CONFIG_ARM64
50 #include <asm/armv8/mmu.h>
51
52 static struct mm_region rk3528_mem_map[] = {
53 {
54 .virt = 0x0UL,
55 .phys = 0x0UL,
56 .size = 0xfc000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
58 PTE_BLOCK_INNER_SHARE
59 }, {
60 .virt = 0xfc000000UL,
61 .phys = 0xfc000000UL,
62 .size = 0x04000000UL,
63 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
64 PTE_BLOCK_NON_SHARE |
65 PTE_BLOCK_PXN | PTE_BLOCK_UXN
66 }, {
67 /* List terminator */
68 0,
69 }
70 };
71
72 struct mm_region *mem_map = rk3528_mem_map;
73 #endif
74
75 #define GPIO0_IOC_BASE 0xFF540000
76 #define GPIO1_IOC_BASE 0xFF560000
77 #define GPIO2_IOC_BASE 0xFF570000
78 #define GPIO3_IOC_BASE 0xFF560000
79 #define GPIO4_IOC_BASE 0xFF550000
80
81 #define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)
82 #define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)
83 #define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)
84 #define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)
85 #define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)
86 #define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)
87
88 /* uart0 iomux */
89 /* gpio4c7 */
90 #define UART0_RX_M0 1
91 #define UART0_RX_M0_OFFSET 12
92 #define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)
93 /* gpio4d0 */
94 #define UART0_TX_M0 1
95 #define UART0_TX_M0_OFFSET 0
96 #define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)
97
98 /* gpio2a0 */
99 #define UART0_RX_M1 2
100 #define UART0_RX_M1_OFFSET 0
101 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
102 /* gpio2a1 */
103 #define UART0_TX_M1 2
104 #define UART0_TX_M1_OFFSET 4
105 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
106
107 /* uart1 iomux */
108 /* gpio4a7 */
109 #define UART1_RX_M0 2
110 #define UART1_RX_M0_OFFSET 12
111 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
112 /* gpio4a6 */
113 #define UART1_TX_M0 2
114 #define UART1_TX_M0_OFFSET 8
115 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
116
117 /* gpio4c6 */
118 #define UART1_RX_M1 2
119 #define UART1_RX_M1_OFFSET 8
120 #define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
121 /* gpio4c5 */
122 #define UART1_TX_M1 2
123 #define UART1_TX_M1_OFFSET 4
124 #define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
125
126 /* uart2 iomux */
127 /* gpio3a0 */
128 #define UART2_RX_M0 1
129 #define UART2_RX_M0_OFFSET 0
130 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
131 /* gpio3a1 */
132 #define UART2_TX_M0 1
133 #define UART2_TX_M0_OFFSET 4
134 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
135
136 /* gpio1b0 */
137 #define UART2_RX_M1 1
138 #define UART2_RX_M1_OFFSET 0
139 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
140 /* gpio1b1 */
141 #define UART2_TX_M1 1
142 #define UART2_TX_M1_OFFSET 4
143 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
144
145 /* uart3 iomux */
146 /* gpio4b0 */
147 #define UART3_RX_M0 2
148 #define UART3_RX_M0_OFFSET 0
149 #define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
150 /* gpio4b1 */
151 #define UART3_TX_M0 2
152 #define UART3_TX_M0_OFFSET 4
153 #define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
154
155 /* gpio4b7 */
156 #define UART3_RX_M1 3
157 #define UART3_RX_M1_OFFSET 12
158 #define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)
159 /* gpio4c0 */
160 #define UART3_TX_M1 3
161 #define UART3_TX_M1_OFFSET 0
162 #define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
163
164 /* uart4 iomux */
165 /* gpio2a2 */
166 #define UART4_RX_M0 3
167 #define UART4_RX_M0_OFFSET 8
168 #define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
169 /* gpio2a3 */
170 #define UART4_TX_M0 3
171 #define UART4_TX_M0_OFFSET 12
172 #define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
173
174 /* uart5 iomux */
175 /* gpio1a2 */
176 #define UART5_RX_M0 2
177 #define UART5_RX_M0_OFFSET 8
178 #define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
179 /* gpio1a3 */
180 #define UART5_TX_M0 2
181 #define UART5_TX_M0_OFFSET 12
182 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
183
184 /* gpio1d4 */
185 #define UART5_RX_M1 2
186 #define UART5_RX_M1_OFFSET 0
187 #define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
188 /* gpio1d7 */
189 #define UART5_TX_M1 2
190 #define UART5_TX_M1_OFFSET 12
191 #define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
192
193 /* uart6 iomux */
194 /* gpio3a7 */
195 #define UART6_RX_M0 4
196 #define UART6_RX_M0_OFFSET 12
197 #define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
198 /* gpio3a6 */
199 #define UART6_TX_M0 4
200 #define UART6_TX_M0_OFFSET 8
201 #define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
202
203 /* gpio3c3 */
204 #define UART6_RX_M1 4
205 #define UART6_RX_M1_OFFSET 12
206 #define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
207 /* gpio3c1 */
208 #define UART6_TX_M1 4
209 #define UART6_TX_M1_OFFSET 4
210 #define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
211
212 /* uart7 iomux */
213 /* gpio3b3 */
214 #define UART7_RX_M0 4
215 #define UART7_RX_M0_OFFSET 12
216 #define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
217 /* gpio3b2 */
218 #define UART7_TX_M0 4
219 #define UART7_TX_M0_OFFSET 8
220 #define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
221
222 /* gpio1b3 */
223 #define UART7_RX_M1 4
224 #define UART7_RX_M1_OFFSET 12
225 #define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
226 /* gpio1b2 */
227 #define UART7_TX_M1 4
228 #define UART7_TX_M1_OFFSET 8
229 #define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
230
231
232 #define set_uart_iomux(bits_offset, bits_val, addr) \
233 writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
234
235 #define set_uart_iomux_rx(ID, MODE) \
236 set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
237 #define set_uart_iomux_tx(ID, MODE) \
238 set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
239
board_debug_uart_init(void)240 void board_debug_uart_init(void)
241 {
242 /* UART 0 */
243 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)
244 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
245 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
246
247 /* UART0_M0 Switch iomux */
248 set_uart_iomux_rx(0, 0);
249 set_uart_iomux_tx(0, 0);
250 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
251 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
252
253 /* UART0_M1 Switch iomux */
254 set_uart_iomux_rx(0, 1);
255 set_uart_iomux_tx(0, 1);
256 #endif
257 /* UART 1 */
258 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)
259 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
260 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
261
262 /* UART1_M0 Switch iomux */
263 set_uart_iomux_rx(1, 0);
264 set_uart_iomux_tx(1, 0);
265 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
266 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
267
268 /* UART1_M1 Switch iomux */
269 set_uart_iomux_rx(1, 1);
270 set_uart_iomux_tx(1, 1);
271 #endif
272 /* UART 2 */
273 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)
274 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
275 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
276
277 /* UART2_M0 Switch iomux */
278 set_uart_iomux_rx(2, 0);
279 set_uart_iomux_tx(2, 0);
280 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
281 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
282
283 /* UART2_M1 Switch iomux */
284 set_uart_iomux_rx(2, 1);
285 set_uart_iomux_tx(2, 1);
286 #endif
287 /* UART 3 */
288 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)
289 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
290 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
291
292 /* UART3_M0 Switch iomux */
293 set_uart_iomux_rx(3, 0);
294 set_uart_iomux_tx(3, 0);
295 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
296 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
297
298 /* UART3_M1 Switch iomux */
299 set_uart_iomux_rx(3, 1);
300 set_uart_iomux_tx(3, 1);
301 #endif
302 /* UART 4 */
303 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)
304 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
305 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
306
307 /* UART4_M0 Switch iomux */
308 set_uart_iomux_rx(4, 0);
309 set_uart_iomux_tx(4, 0);
310 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
311 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
312
313 /* UART4_M1 Switch iomux */
314 set_uart_iomux_rx(4, 1);
315 set_uart_iomux_tx(4, 1);
316 #endif
317 /* UART 5 */
318 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)
319 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
320 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
321
322 /* UART5_M0 Switch iomux */
323 set_uart_iomux_rx(5, 0);
324 set_uart_iomux_tx(5, 0);
325 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
326 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
327
328 /* UART5_M1 Switch iomux */
329 set_uart_iomux_rx(5, 1);
330 set_uart_iomux_tx(5, 1);
331 #endif
332 /* UART 6 */
333 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)
334 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
335 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
336
337 /* UART6_M0 Switch iomux */
338 set_uart_iomux_rx(6, 0);
339 set_uart_iomux_tx(6, 0);
340 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
341 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
342
343 /* UART6_M1 Switch iomux */
344 set_uart_iomux_rx(6, 1);
345 set_uart_iomux_tx(6, 1);
346 #endif
347 /* UART 7 */
348 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)
349 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
350 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
351
352 /* UART7_M0 Switch iomux */
353 set_uart_iomux_rx(7, 0);
354 set_uart_iomux_tx(7, 0);
355 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
356 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
357
358 /* UART7_M1 Switch iomux */
359 set_uart_iomux_rx(7, 1);
360 set_uart_iomux_tx(7, 1);
361 #endif
362 #endif
363 }
364
365 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)366 void rockchip_stimer_init(void)
367 {
368 /* If Timer already enabled, don't re-init it */
369 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
370
371 if (reg & 0x1)
372 return;
373
374 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
375 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
376 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
377 dsb();
378 writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
379 }
380 #endif
381
arch_cpu_init(void)382 int arch_cpu_init(void)
383 {
384 #if defined(CONFIG_SPL_BUILD)
385 u32 val;
386
387 /*
388 * Select clk_tx source as default for i2s2/i2s3
389 * Set I2Sx_MCLK as input default
390 *
391 * It's safe to set mclk as input default to avoid high freq glitch
392 * which may make devices work unexpected. And then enabled by
393 * kernel stage or any state where user use it.
394 */
395 writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);
396 writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);
397
398 /* Set the emmc to access ddr memory */
399 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
400 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
401
402 /* Set the sdmmc to access ddr memory */
403 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
404 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
405
406 /* Set the crypto to access ddr memory */
407 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
408 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
409
410 #if defined(CONFIG_ROCKCHIP_SFC)
411 /* Set the fspi to access ddr memory */
412 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
413 writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
414 #endif
415
416 #ifndef CONFIG_TPL_BUILD
417 /* Set cpu qos priority, then
418 * Peri > VOP > CPU = RKVDEC/RKVENC/VPU > GPU/RGA/Other
419 */
420 writel(QOS_PRIORITY_LEVEL(2, 2), CPU_PRIORITY_REG);
421 #endif
422
423 if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {
424 /*
425 * set the emmc io drive strength:
426 * data and cmd: level 3
427 * clock: level 5
428 */
429 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);
430 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);
431 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);
432 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);
433 writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);
434 }
435
436 #elif defined(CONFIG_SUPPORT_USBPLUG)
437 u32 val;
438
439 /* Set the usb to access ddr memory */
440 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
441 writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
442
443 /* Set the emmc to access ddr memory */
444 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
445 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
446
447 /* Set emmc iomux */
448 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
449 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
450 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
451
452 #if defined(CONFIG_ROCKCHIP_SFC)
453 /* Set the fspi to access ddr memory */
454 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
455 writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
456
457 /* Set fspi iomux */
458 writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
459 writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
460 writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
461 #endif
462
463 #endif
464 return 0;
465 }
466
467 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)468 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
469 {
470 u32 val;
471
472 /* open clk_pmu_mcu_jtag / clk_mcu_32k_en / fclk_mcu_en */
473 writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);
474 /* set the mcu to access ddr memory */
475 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
476 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
477 /* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */
478 /* set the mcu to secure */
479 writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);
480 /* open mcu_debug_en / mcu_dclk_en / mcu_hclk_en / mcu_sclk_en */
481 writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);
482 /* set start addr, mcu_code_addr_start */
483 writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);
484 /* mcu_tcm_addr_start, multiplex pmu sram address */
485 writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);
486 /* jtag_mcu_m0 gpio2a4/gpio2a5 iomux */
487 /* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */
488 /* release the mcu */
489 writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);
490
491 return 0;
492 }
493 #endif
494
495