Searched refs:FSL_DDR_CS0_CS1_CS2_CS3 (Results 1 – 5 of 5) sorted by relevance
721 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()727 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()731 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()1204 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; in populate_memctl_options()1210 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in populate_memctl_options()1211 case FSL_DDR_CS0_CS1_CS2_CS3: in populate_memctl_options()
315 FSL_DDR_CS0_CS1_CS2_CS3) { in __step_assign_addresses()316 case FSL_DDR_CS0_CS1_CS2_CS3: in __step_assign_addresses()
307 case FSL_DDR_CS0_CS1_CS2_CS3: in print_ddr_info()
2390 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()2391 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()2416 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()2417 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) macro