Searched refs:FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK (Results 1 – 6 of 6) sorted by relevance
49 cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()80 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in get_serdes_protocol()177 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()358 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()409 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, in fsl_serdes_init()
27 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
263 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in fdt_fixup_board_enet()305 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
263 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
234 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 macro