1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <asm/io.h>
8*4882a593Smuzhiyun #include <netdev.h>
9*4882a593Smuzhiyun #include <fm_eth.h>
10*4882a593Smuzhiyun #include <fsl_dtsec.h>
11*4882a593Smuzhiyun #include <fsl_mdio.h>
12*4882a593Smuzhiyun #include <malloc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "../common/fman.h"
15*4882a593Smuzhiyun
board_eth_init(bd_t * bis)16*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun #ifdef CONFIG_FMAN_ENET
19*4882a593Smuzhiyun int i;
20*4882a593Smuzhiyun struct memac_mdio_info dtsec_mdio_info;
21*4882a593Smuzhiyun struct memac_mdio_info tgec_mdio_info;
22*4882a593Smuzhiyun struct mii_dev *dev;
23*4882a593Smuzhiyun u32 srds_s1;
24*4882a593Smuzhiyun struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun srds_s1 = in_be32(&gur->rcwsr[4]) &
27*4882a593Smuzhiyun FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
28*4882a593Smuzhiyun srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun dtsec_mdio_info.regs =
31*4882a593Smuzhiyun (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Register the 1G MDIO bus */
36*4882a593Smuzhiyun fm_memac_mdio_init(bis, &dtsec_mdio_info);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun tgec_mdio_info.regs =
39*4882a593Smuzhiyun (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
40*4882a593Smuzhiyun tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Register the 10G MDIO bus */
43*4882a593Smuzhiyun fm_memac_mdio_init(bis, &tgec_mdio_info);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Set the two on-board RGMII PHY address */
46*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
47*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Set the two on-board SGMII PHY address */
50*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
51*4882a593Smuzhiyun fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Set the on-board AQ PHY address */
54*4882a593Smuzhiyun fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun switch (srds_s1) {
57*4882a593Smuzhiyun case 0x1133:
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun default:
60*4882a593Smuzhiyun printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
61*4882a593Smuzhiyun srds_s1);
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
66*4882a593Smuzhiyun for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
67*4882a593Smuzhiyun fm_info_set_mdio(i, dev);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* XFI on lane A, MAC 9 */
70*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
71*4882a593Smuzhiyun fm_info_set_mdio(FM1_10GEC1, dev);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun cpu_eth_init(bis);
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return pci_eth_init(bis);
77*4882a593Smuzhiyun }
78