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Searched refs:DPCD_TRAINING_LANE0_SET (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_dp.c583 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); in exynos_dp_process_clock_recovery()
682 DPCD_TRAINING_LANE0_SET, in exynos_dp_process_equalizer_training()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h469 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h624 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_edp.c485 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, in rk_edp_link_train_cr()