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Searched refs:DIV_TO_RATE (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
165 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
186 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
197 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
222 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio1_get_clk()
248 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio0_get_clk()
283 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_dclk_vop_get_clk()
312 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_bus_get_clk()
340 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_peri_get_clk()
352 return DIV_TO_RATE(parent_rate, div); in rv1108_hclk_peri_get_clk()
[all …]
H A Dclk_rv1126.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
232 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_i2c_get_pmuclk()
285 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pwm_get_pmuclk()
346 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_spi_get_pmuclk()
374 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdpmu_get_pmuclk()
604 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdcore_get_clk()
664 return DIV_TO_RATE(parent, div); in rv1126_pdbus_get_clk()
734 return DIV_TO_RATE(parent, div); in rv1126_pdphp_get_clk()
774 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdaudio_get_clk()
817 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_i2c_get_clk()
[all …]
H A Dclk_rk3328.c25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
194 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_i2c_get_clk()
240 return DIV_TO_RATE(priv->gpll_hz, src_clk_div); in rk3328_i2c_set_clk()
276 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
300 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2phy_src_set_clk()
339 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3328_mmc_get_clk()
341 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk3328_mmc_get_clk()
397 return DIV_TO_RATE(p_rate, div); in rk3328_spi_get_clk()
410 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_spi_set_clk()
422 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_pwm_get_clk()
[all …]
H A Dclk_rk3308.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
223 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
287 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
331 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3308_mmc_get_clk()
333 return DIV_TO_RATE(priv->vpll0_hz, div) / 2; in rk3308_mmc_get_clk()
389 return DIV_TO_RATE(OSC_HZ, div); in rk3308_saradc_get_clk()
417 return DIV_TO_RATE(OSC_HZ, div); in rk3308_tsadc_get_clk()
460 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
504 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
557 return DIV_TO_RATE(parent, div); in rk3308_vop_get_clk()
[all …]
H A Dclk_rk1808.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
130 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_i2c_get_clk()
216 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk1808_mmc_get_clk()
218 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk1808_mmc_get_clk()
276 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_sfc_get_clk()
302 return DIV_TO_RATE(OSC_HZ, div); in rk1808_saradc_get_clk()
344 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_pwm_get_clk()
391 return DIV_TO_RATE(OSC_HZ, div); in rk1808_tsadc_get_clk()
432 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_spi_get_clk()
513 return DIV_TO_RATE(parent, div); in rk1808_vop_get_clk()
[all …]
H A Dclk_px30.c51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
324 return DIV_TO_RATE(priv->gpll_hz, div); in px30_i2c_get_clk()
527 return DIV_TO_RATE(priv->gpll_hz, div); in px30_nandc_get_clk()
575 return DIV_TO_RATE(OSC_HZ, div) / 2; in px30_mmc_get_clk()
577 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in px30_mmc_get_clk()
632 return DIV_TO_RATE(priv->gpll_hz, div); in px30_sfc_get_clk()
669 return DIV_TO_RATE(priv->gpll_hz, div); in px30_pwm_get_clk()
711 return DIV_TO_RATE(OSC_HZ, div); in px30_saradc_get_clk()
737 return DIV_TO_RATE(OSC_HZ, div); in px30_tsadc_get_clk()
774 return DIV_TO_RATE(priv->gpll_hz, div); in px30_spi_get_clk()
[all …]
H A Dclk_rk3588.c22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
298 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
309 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
667 return DIV_TO_RATE(prate, div); in rk3588_adc_get_clk()
678 return DIV_TO_RATE(prate, div); in rk3588_adc_get_clk()
760 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
772 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
782 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
794 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
804 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
[all …]
H A Dclk_rk3562.c20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
231 return DIV_TO_RATE(rate, div); in rk3562_bus_get_rate()
305 return DIV_TO_RATE(rate, div); in rk3562_peri_get_rate()
366 return DIV_TO_RATE(rate, div); in rk3562_i2c_get_rate()
456 return DIV_TO_RATE(priv->cpll_hz, div); in rk3562_uart_get_rate()
463 return DIV_TO_RATE(priv->cpll_hz, div) * n / m; in rk3562_uart_get_rate()
506 return DIV_TO_RATE(p_rate, div); in rk3562_uart_get_rate()
513 return DIV_TO_RATE(p_rate, div) * n / m; in rk3562_uart_get_rate()
639 return DIV_TO_RATE(rate, div); in rk3562_pwm_get_rate()
741 return DIV_TO_RATE(rate, div); in rk3562_spi_get_rate()
[all …]
H A Dclk_rk3288.c210 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
468 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
746 return DIV_TO_RATE(src_rate, div) / 2; in rockchip_mmc_get_clk()
826 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()
876 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_peri_get_clk()
894 parent_rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
897 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
925 rate = DIV_TO_RATE(parent_rate, div); in rockchip_pclk_cpu_get_clk()
954 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
979 return DIV_TO_RATE(32768, div); in rockchip_tsadc_get_clk()
[all …]
H A Dclk_rk3399.c46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
618 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_i2c_get_clk()
717 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_spi_get_clk()
821 return DIV_TO_RATE(OSC_HZ, div); in rk3399_mmc_get_clk()
823 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_mmc_get_clk()
966 return DIV_TO_RATE(OSC_HZ, div); in rk3399_saradc_get_clk()
991 return DIV_TO_RATE(OSC_HZ, div); in rk3399_tsadc_get_clk()
1029 return DIV_TO_RATE(parent, div); in rk3399_crypto_get_clk()
1125 return DIV_TO_RATE(parent, div); in rk3399_peri_get_clk()
1137 return DIV_TO_RATE(parent, div); in rk3399_alive_get_clk()
[all …]
H A Dclk_rk3036.c47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
267 return DIV_TO_RATE(src_rate, div) / 2; in rockchip_mmc_get_clk()
318 return DIV_TO_RATE(clk_general_rate, div); in rk3036_spi_get_clk()
349 return DIV_TO_RATE(parent, div); in rockchip_dclk_lcdc_get_clk()
381 return DIV_TO_RATE(parent, div); in rockchip_aclk_lcdc_get_clk()
422 return DIV_TO_RATE(parent, div); in rk3036_peri_get_clk()
H A Dclk_rk3128.c23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
174 return DIV_TO_RATE(src_rate, div); in rockchip_mmc_get_clk()
255 return DIV_TO_RATE(parent, div); in rk3128_peri_get_clk()
330 return DIV_TO_RATE(parent, div); in rk3128_bus_get_clk()
383 return DIV_TO_RATE(parent, div); in rk3128_spi_get_clk()
410 return DIV_TO_RATE(OSC_HZ, div); in rk3128_saradc_get_clk()
496 return DIV_TO_RATE(parent, div); in rk3128_vop_get_rate()
507 return DIV_TO_RATE(rk3128_bus_get_clk(priv, ACLK_CPU), div); in rk3128_crypto_get_rate()
H A Dclk_rv1106.c23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
393 return DIV_TO_RATE(prate, div); in rv1106_mmc_get_clk()
405 return DIV_TO_RATE(prate, div); in rv1106_mmc_get_clk()
421 return DIV_TO_RATE(prate, div); in rv1106_mmc_get_clk()
702 return DIV_TO_RATE(OSC_HZ, div); in rv1106_adc_get_clk()
707 return DIV_TO_RATE(OSC_HZ, div); in rv1106_adc_get_clk()
711 return DIV_TO_RATE(OSC_HZ, div); in rv1106_adc_get_clk()
845 return DIV_TO_RATE(p_rate, div); in rv1106_uart_get_rate()
852 return DIV_TO_RATE(p_rate, div) * n / m; in rv1106_uart_get_rate()
949 return DIV_TO_RATE(priv->gpll_hz, div); in rv1106_vop_get_clk()
[all …]
H A Dclk_rk3368.c62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
481 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
533 return DIV_TO_RATE(GPLL_HZ, div); in rk3368_spi_get_clk()
571 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
616 return DIV_TO_RATE(parent, div); in rk3368_bus_get_clk()
690 return DIV_TO_RATE(parent, div); in rk3368_peri_get_clk()
765 return DIV_TO_RATE(parent, div); in rk3368_vop_get_clk()
834 return DIV_TO_RATE(parent, div); in rk3368_alive_get_clk()
845 return DIV_TO_RATE(rk3368_bus_get_clk(priv->cru, ACLK_BUS), div); in rk3368_crypto_get_rate()
H A Dclk_rk322x.c22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
176 return DIV_TO_RATE(src_rate, div) / 2; in rk322x_mmc_get_clk()
210 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
300 return DIV_TO_RATE(parent, div); in rk322x_bus_get_clk()
373 return DIV_TO_RATE(parent, div); in rk322x_peri_get_clk()
430 return DIV_TO_RATE(parent, div); in rk322x_spi_get_clk()
483 return DIV_TO_RATE(parent, div); in rk322x_vop_get_clk()
544 return DIV_TO_RATE(parent, div); in rk322x_crypto_get_clk()
H A Dclk_rk3528.c21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
275 return DIV_TO_RATE(priv->ppll_hz, div); in rk3528_ppll_matrix_get_rate()
428 return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div); in rk3528_cgpll_matrix_get_rate()
871 return DIV_TO_RATE(OSC_HZ, div); in rk3528_adc_get_clk()
925 return DIV_TO_RATE(prate, div); in rk3528_sdmmc_get_clk()
972 return DIV_TO_RATE(parent, div); in rk3528_sfc_get_clk()
1019 return DIV_TO_RATE(parent, div); in rk3528_emmc_get_clk()
1086 return DIV_TO_RATE(prate, div); in rk3528_dclk_vop_get_clk()
1217 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3528_uart_get_rate()
1222 rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m; in rk3528_uart_get_rate()
H A Dclk_rk3188.c91 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
304 return DIV_TO_RATE(gclk_rate, div) / 2; in rockchip_mmc_get_clk()
362 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()
398 return DIV_TO_RATE(OSC_HZ, div); in rk3188_saradc_get_clk()
H A Dclk_rk3568.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
259 return DIV_TO_RATE(priv->ppll_hz, div); in rk3568_i2c_get_pmuclk()
303 return DIV_TO_RATE(parent, div); in rk3568_pwm_get_pmuclk()
349 return DIV_TO_RATE(parent, div); in rk3568_pmu_get_pmuclk()
668 return DIV_TO_RATE(priv->cpll_hz, div); in rk3568_cpll_div_get_rate()
1239 return DIV_TO_RATE(prate, div); in rk3568_adc_get_clk()
1244 return DIV_TO_RATE(prate, div); in rk3568_adc_get_clk()
1750 return DIV_TO_RATE(parent, div); in rk3568_aclk_vop_get_clk()
1808 return DIV_TO_RATE(parent, div); in rk3568_dclk_vop_get_clk()
2087 p_rate = DIV_TO_RATE(priv->cpll_hz, div); in rk3568_ebc_get_clk()
[all …]
H A Dclk_rk3066.c93 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
303 return DIV_TO_RATE(gclk_rate, div); in rockchip_mmc_get_clk()
358 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()