Searched refs:DCLK_VOP_PLL_SEL_MASK (Results 1 – 7 of 7) sorted by relevance
159 DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8), enumerator
243 DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, enumerator
208 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, enumerator
249 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, enumerator781 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { in rk3399_vop_set_clk()1345 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, in rk3399_dclk_vop_set_parent()1348 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, in rk3399_dclk_vop_set_parent()
532 pll_sel = (con & DCLK_VOP_PLL_SEL_MASK) >> DCLK_VOP_PLL_SEL_SHIFT; in rk3308_vop_get_clk()602 DCLK_VOP_SEL_MASK | DCLK_VOP_PLL_SEL_MASK | in rk3308_vop_set_clk()
294 DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK | in rv1108_dclk_vop_set_clk()
788 (DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT) | in rk3368_vop_set_clk()