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Searched refs:CS_ENABLE_REG (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_centralization.c89 CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
93 CS_ENABLE_REG, (1 << 3), (1 << 3))); in ddr3_tip_centralization()
486 if_id, CS_ENABLE_REG, in ddr3_tip_centralization()
523 if_id, CS_ENABLE_REG, in ddr3_tip_special_rx()
528 if_id, CS_ENABLE_REG, in ddr3_tip_special_rx()
H A Dddr3_training_leveling.c164 CS_ENABLE_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
169 CS_ENABLE_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
421 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
565 CS_ENABLE_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
570 CS_ENABLE_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
900 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
992 CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
1284 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
H A Dddr3_a38x.c330 reg = reg_read(CS_ENABLE_REG); in ddr3_tip_a38x_select_ddr_controller()
337 reg_write(CS_ENABLE_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
H A Dddr3_training_ip_engine.c217 CS_ENABLE_REG, 1 << 3, 1 << 3)); in ddr3_tip_ip_training()
226 CS_ENABLE_REG, 0, 1 << 3)); in ddr3_tip_ip_training()
609 (dev_num, ACCESS_TYPE_UNICAST, if_id, CS_ENABLE_REG, in ddr3_tip_read_training_result()
753 CS_ENABLE_REG, (1 << 3), (1 << 3))); in ddr3_tip_load_all_pattern_to_mem()
H A Dddr3_training_pbs.c67 CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
72 CS_ENABLE_REG, (1 << 3), (1 << 3))); in ddr3_tip_pbs()
872 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()
H A Dddr3_training_ip_flow.h158 #define CS_ENABLE_REG 0x16d8 macro
H A Dddr3_training.c346 if_id, CS_ENABLE_REG, 0, in hws_ddr3_tip_init_controller()
1314 CS_ENABLE_REG, 0, 0x8)); in ddr3_tip_freq_set()
1570 CS_ENABLE_REG, in ddr3_tip_freq_set()
2468 if_id, CS_ENABLE_REG, 1 << 3, in ddr3_tip_enable_init_sequence()