Searched refs:CLK_REF_PIPE_PHY1 (Results 1 – 6 of 6) sorted by relevance
500 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>;502 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
1437 case CLK_REF_PIPE_PHY1: in rk3588_pciephy_get_rate()1482 case CLK_REF_PIPE_PHY1: in rk3588_pciephy_set_rate()1644 case CLK_REF_PIPE_PHY1: in rk3588_clk_get_rate()1793 case CLK_REF_PIPE_PHY1: in rk3588_clk_set_rate()
823 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,826 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
696 #define CLK_REF_PIPE_PHY1 702 macro
698 #define CLK_REF_PIPE_PHY1 702 macro
2125 MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT,