1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 9 10 /* cru-clocks indices */ 11 12 /* cru plls */ 13 #define PLL_B0PLL 1 14 #define PLL_B1PLL 2 15 #define PLL_LPLL 3 16 #define PLL_V0PLL 4 17 #define PLL_AUPLL 5 18 #define PLL_CPLL 6 19 #define PLL_GPLL 7 20 #define PLL_NPLL 8 21 #define PLL_PPLL 9 22 #define ARMCLK_L 10 23 #define ARMCLK_B01 11 24 #define ARMCLK_B23 12 25 26 /* cru clocks */ 27 #define PCLK_BIGCORE0_ROOT 20 28 #define PCLK_BIGCORE0_PVTM 21 29 #define PCLK_BIGCORE1_ROOT 22 30 #define PCLK_BIGCORE1_PVTM 23 31 #define PCLK_DSU_S_ROOT 24 32 #define PCLK_DSU_ROOT 25 33 #define PCLK_DSU_NS_ROOT 26 34 #define PCLK_LITCORE_PVTM 27 35 #define PCLK_DBG 28 36 #define PCLK_DSU 29 37 #define PCLK_S_DAPLITE 30 38 #define PCLK_M_DAPLITE 31 39 #define MBIST_MCLK_PDM1 32 40 #define MBIST_CLK_ACDCDIG 33 41 #define HCLK_I2S2_2CH 34 42 #define HCLK_I2S3_2CH 35 43 #define CLK_I2S2_2CH_SRC 36 44 #define CLK_I2S2_2CH_FRAC 37 45 #define CLK_I2S2_2CH 38 46 #define MCLK_I2S2_2CH 39 47 #define I2S2_2CH_MCLKOUT 40 48 #define CLK_DAC_ACDCDIG 41 49 #define CLK_I2S3_2CH_SRC 42 50 #define CLK_I2S3_2CH_FRAC 43 51 #define CLK_I2S3_2CH 44 52 #define MCLK_I2S3_2CH 45 53 #define I2S3_2CH_MCLKOUT 46 54 #define PCLK_ACDCDIG 47 55 #define HCLK_I2S0_8CH 48 56 #define CLK_I2S0_8CH_TX_SRC 49 57 #define CLK_I2S0_8CH_TX_FRAC 50 58 #define MCLK_I2S0_8CH_TX 51 59 #define CLK_I2S0_8CH_TX 52 60 #define CLK_I2S0_8CH_RX_SRC 53 61 #define CLK_I2S0_8CH_RX_FRAC 54 62 #define MCLK_I2S0_8CH_RX 55 63 #define CLK_I2S0_8CH_RX 56 64 #define I2S0_8CH_MCLKOUT 57 65 #define HCLK_PDM1 58 66 #define MCLK_PDM1 59 67 #define HCLK_AUDIO_ROOT 60 68 #define PCLK_AUDIO_ROOT 61 69 #define HCLK_SPDIF0 62 70 #define CLK_SPDIF0_SRC 63 71 #define CLK_SPDIF0_FRAC 64 72 #define MCLK_SPDIF0 65 73 #define CLK_SPDIF0 66 74 #define CLK_SPDIF1 67 75 #define HCLK_SPDIF1 68 76 #define CLK_SPDIF1_SRC 69 77 #define CLK_SPDIF1_FRAC 70 78 #define MCLK_SPDIF1 71 79 #define ACLK_AV1_ROOT 72 80 #define ACLK_AV1 73 81 #define PCLK_AV1_ROOT 74 82 #define PCLK_AV1 75 83 #define PCLK_MAILBOX0 76 84 #define PCLK_MAILBOX1 77 85 #define PCLK_MAILBOX2 78 86 #define PCLK_PMU2 79 87 #define PCLK_PMUCM0_INTMUX 80 88 #define PCLK_DDRCM0_INTMUX 81 89 #define PCLK_TOP 82 90 #define PCLK_PWM1 83 91 #define CLK_PWM1 84 92 #define CLK_PWM1_CAPTURE 85 93 #define PCLK_PWM2 86 94 #define CLK_PWM2 87 95 #define CLK_PWM2_CAPTURE 88 96 #define PCLK_PWM3 89 97 #define CLK_PWM3 90 98 #define CLK_PWM3_CAPTURE 91 99 #define PCLK_BUSTIMER0 92 100 #define PCLK_BUSTIMER1 93 101 #define CLK_BUS_TIMER_ROOT 94 102 #define CLK_BUSTIMER0 95 103 #define CLK_BUSTIMER1 96 104 #define CLK_BUSTIMER2 97 105 #define CLK_BUSTIMER3 98 106 #define CLK_BUSTIMER4 99 107 #define CLK_BUSTIMER5 100 108 #define CLK_BUSTIMER6 101 109 #define CLK_BUSTIMER7 102 110 #define CLK_BUSTIMER8 103 111 #define CLK_BUSTIMER9 104 112 #define CLK_BUSTIMER10 105 113 #define CLK_BUSTIMER11 106 114 #define PCLK_WDT0 107 115 #define TCLK_WDT0 108 116 #define PCLK_CAN0 111 117 #define CLK_CAN0 112 118 #define PCLK_CAN1 113 119 #define CLK_CAN1 114 120 #define PCLK_CAN2 115 121 #define CLK_CAN2 116 122 #define ACLK_DECOM 117 123 #define PCLK_DECOM 118 124 #define DCLK_DECOM 119 125 #define ACLK_DMAC0 120 126 #define ACLK_DMAC1 121 127 #define ACLK_DMAC2 122 128 #define ACLK_BUS_ROOT 123 129 #define ACLK_GIC 124 130 #define PCLK_GPIO1 125 131 #define DBCLK_GPIO1 126 132 #define PCLK_GPIO2 127 133 #define DBCLK_GPIO2 128 134 #define PCLK_GPIO3 129 135 #define DBCLK_GPIO3 130 136 #define PCLK_GPIO4 131 137 #define DBCLK_GPIO4 132 138 #define PCLK_I2C1 133 139 #define PCLK_I2C2 134 140 #define PCLK_I2C3 135 141 #define PCLK_I2C4 136 142 #define PCLK_I2C5 137 143 #define PCLK_I2C6 138 144 #define PCLK_I2C7 139 145 #define PCLK_I2C8 140 146 #define CLK_I2C1 141 147 #define CLK_I2C2 142 148 #define CLK_I2C3 143 149 #define CLK_I2C4 144 150 #define CLK_I2C5 145 151 #define CLK_I2C6 146 152 #define CLK_I2C7 147 153 #define CLK_I2C8 148 154 #define PCLK_OTPC_NS 149 155 #define CLK_OTPC_NS 150 156 #define CLK_OTPC_ARB 151 157 #define CLK_OTPC_AUTO_RD_G 152 158 #define CLK_OTP_PHY_G 153 159 #define PCLK_SARADC 156 160 #define CLK_SARADC 157 161 #define PCLK_SPI0 158 162 #define PCLK_SPI1 159 163 #define PCLK_SPI2 160 164 #define PCLK_SPI3 161 165 #define PCLK_SPI4 162 166 #define CLK_SPI0 163 167 #define CLK_SPI1 164 168 #define CLK_SPI2 165 169 #define CLK_SPI3 166 170 #define CLK_SPI4 167 171 #define ACLK_SPINLOCK 168 172 #define PCLK_TSADC 169 173 #define CLK_TSADC 170 174 #define PCLK_UART1 171 175 #define PCLK_UART2 172 176 #define PCLK_UART3 173 177 #define PCLK_UART4 174 178 #define PCLK_UART5 175 179 #define PCLK_UART6 176 180 #define PCLK_UART7 177 181 #define PCLK_UART8 178 182 #define PCLK_UART9 179 183 #define CLK_UART1_SRC 180 184 #define CLK_UART1_FRAC 181 185 #define CLK_UART1 182 186 #define SCLK_UART1 183 187 #define CLK_UART2_SRC 184 188 #define CLK_UART2_FRAC 185 189 #define CLK_UART2 186 190 #define SCLK_UART2 187 191 #define CLK_UART3_SRC 188 192 #define CLK_UART3_FRAC 189 193 #define CLK_UART3 190 194 #define SCLK_UART3 191 195 #define CLK_UART4_SRC 192 196 #define CLK_UART4_FRAC 193 197 #define CLK_UART4 194 198 #define SCLK_UART4 195 199 #define CLK_UART5_SRC 196 200 #define CLK_UART5_FRAC 197 201 #define CLK_UART5 198 202 #define SCLK_UART5 199 203 #define CLK_UART6_SRC 200 204 #define CLK_UART6_FRAC 201 205 #define CLK_UART6 202 206 #define SCLK_UART6 203 207 #define CLK_UART7_SRC 204 208 #define CLK_UART7_FRAC 205 209 #define CLK_UART7 206 210 #define SCLK_UART7 207 211 #define CLK_UART8_SRC 208 212 #define CLK_UART8_FRAC 209 213 #define CLK_UART8 210 214 #define SCLK_UART8 211 215 #define CLK_UART9_SRC 212 216 #define CLK_UART9_FRAC 213 217 #define CLK_UART9 214 218 #define SCLK_UART9 215 219 #define ACLK_CENTER_ROOT 216 220 #define ACLK_CENTER_LOW_ROOT 217 221 #define HCLK_CENTER_ROOT 218 222 #define PCLK_CENTER_ROOT 219 223 #define ACLK_DMA2DDR 220 224 #define ACLK_DDR_SHAREMEM 221 225 #define ACLK_CENTER_S200_ROOT 222 226 #define ACLK_CENTER_S400_ROOT 223 227 #define FCLK_DDR_CM0_CORE 224 228 #define CLK_DDR_TIMER_ROOT 225 229 #define CLK_DDR_TIMER0 226 230 #define CLK_DDR_TIMER1 227 231 #define TCLK_WDT_DDR 228 232 #define CLK_DDR_CM0_RTC 228 233 #define PCLK_WDT 230 234 #define PCLK_TIMER 231 235 #define PCLK_DMA2DDR 232 236 #define PCLK_SHAREMEM 233 237 #define CLK_50M_SRC 234 238 #define CLK_100M_SRC 235 239 #define CLK_150M_SRC 236 240 #define CLK_200M_SRC 237 241 #define CLK_250M_SRC 238 242 #define CLK_300M_SRC 239 243 #define CLK_350M_SRC 240 244 #define CLK_400M_SRC 241 245 #define CLK_450M_SRC 242 246 #define CLK_500M_SRC 243 247 #define CLK_600M_SRC 244 248 #define CLK_650M_SRC 245 249 #define CLK_700M_SRC 246 250 #define CLK_800M_SRC 247 251 #define CLK_1000M_SRC 248 252 #define CLK_1200M_SRC 249 253 #define ACLK_TOP_M300_ROOT 250 254 #define ACLK_TOP_M500_ROOT 251 255 #define ACLK_TOP_M400_ROOT 252 256 #define ACLK_TOP_S200_ROOT 253 257 #define ACLK_TOP_S400_ROOT 254 258 #define CLK_MIPI_CAMARAOUT_M0 255 259 #define CLK_MIPI_CAMARAOUT_M1 256 260 #define CLK_MIPI_CAMARAOUT_M2 257 261 #define CLK_MIPI_CAMARAOUT_M3 258 262 #define CLK_MIPI_CAMARAOUT_M4 259 263 #define MCLK_GMAC0_OUT 260 264 #define REFCLKO25M_ETH0_OUT 261 265 #define REFCLKO25M_ETH1_OUT 262 266 #define CLK_CIFOUT_OUT 263 267 #define PCLK_MIPI_DCPHY0 264 268 #define PCLK_MIPI_DCPHY1 265 269 #define PCLK_CSIPHY0 268 270 #define PCLK_CSIPHY1 269 271 #define ACLK_TOP_ROOT 270 272 #define PCLK_TOP_ROOT 271 273 #define ACLK_LOW_TOP_ROOT 272 274 #define PCLK_CRU 273 275 #define PCLK_GPU_ROOT 274 276 #define CLK_GPU_SRC 275 277 #define CLK_GPU 276 278 #define CLK_GPU_COREGROUP 277 279 #define CLK_GPU_STACKS 278 280 #define PCLK_GPU_PVTM 279 281 #define CLK_GPU_PVTM 280 282 #define CLK_CORE_GPU_PVTM 281 283 #define PCLK_GPU_GRF 282 284 #define ACLK_ISP1_ROOT 283 285 #define HCLK_ISP1_ROOT 284 286 #define CLK_ISP1_CORE 285 287 #define CLK_ISP1_CORE_MARVIN 286 288 #define CLK_ISP1_CORE_VICAP 287 289 #define ACLK_ISP1 288 290 #define HCLK_ISP1 289 291 #define ACLK_NPU1 290 292 #define HCLK_NPU1 291 293 #define ACLK_NPU2 292 294 #define HCLK_NPU2 293 295 #define HCLK_NPU_CM0_ROOT 294 296 #define FCLK_NPU_CM0_CORE 295 297 #define CLK_NPU_CM0_RTC 296 298 #define PCLK_NPU_PVTM 297 299 #define PCLK_NPU_GRF 298 300 #define CLK_NPU_PVTM 299 301 #define CLK_CORE_NPU_PVTM 300 302 #define ACLK_NPU0 301 303 #define HCLK_NPU0 302 304 #define HCLK_NPU_ROOT 303 305 #define CLK_NPU_DSU0 304 306 #define PCLK_NPU_ROOT 305 307 #define PCLK_NPU_TIMER 306 308 #define CLK_NPUTIMER_ROOT 307 309 #define CLK_NPUTIMER0 308 310 #define CLK_NPUTIMER1 309 311 #define PCLK_NPU_WDT 310 312 #define TCLK_NPU_WDT 311 313 #define HCLK_EMMC 312 314 #define ACLK_EMMC 313 315 #define CCLK_EMMC 314 316 #define BCLK_EMMC 315 317 #define TMCLK_EMMC 316 318 #define SCLK_SFC 317 319 #define HCLK_SFC 318 320 #define HCLK_SFC_XIP 319 321 #define HCLK_NVM_ROOT 320 322 #define ACLK_NVM_ROOT 321 323 #define CLK_GMAC0_PTP_REF 322 324 #define CLK_GMAC1_PTP_REF 323 325 #define CLK_GMAC_125M 324 326 #define CLK_GMAC_50M 325 327 #define ACLK_PHP_GIC_ITS 326 328 #define ACLK_MMU_PCIE 327 329 #define ACLK_MMU_PHP 328 330 #define ACLK_PCIE_4L_DBI 329 331 #define ACLK_PCIE_2L_DBI 330 332 #define ACLK_PCIE_1L0_DBI 331 333 #define ACLK_PCIE_1L1_DBI 332 334 #define ACLK_PCIE_1L2_DBI 333 335 #define ACLK_PCIE_4L_MSTR 334 336 #define ACLK_PCIE_2L_MSTR 335 337 #define ACLK_PCIE_1L0_MSTR 336 338 #define ACLK_PCIE_1L1_MSTR 337 339 #define ACLK_PCIE_1L2_MSTR 338 340 #define ACLK_PCIE_4L_SLV 339 341 #define ACLK_PCIE_2L_SLV 340 342 #define ACLK_PCIE_1L0_SLV 341 343 #define ACLK_PCIE_1L1_SLV 342 344 #define ACLK_PCIE_1L2_SLV 343 345 #define PCLK_PCIE_4L 344 346 #define PCLK_PCIE_2L 345 347 #define PCLK_PCIE_1L0 347 348 #define PCLK_PCIE_1L1 348 349 #define PCLK_PCIE_1L2 349 350 #define CLK_PCIE_AUX0 350 351 #define CLK_PCIE_AUX1 351 352 #define CLK_PCIE_AUX2 352 353 #define CLK_PCIE_AUX3 353 354 #define CLK_PCIE_AUX4 354 355 #define CLK_PIPEPHY0_REF 355 356 #define CLK_PIPEPHY1_REF 356 357 #define CLK_PIPEPHY2_REF 357 358 #define PCLK_PHP_ROOT 358 359 #define PCLK_GMAC0 359 360 #define PCLK_GMAC1 360 361 #define ACLK_PCIE_ROOT 361 362 #define ACLK_PHP_ROOT 362 363 #define ACLK_PCIE_BRIDGE 363 364 #define ACLK_GMAC0 364 365 #define ACLK_GMAC1 365 366 #define CLK_PMALIVE0 366 367 #define CLK_PMALIVE1 367 368 #define CLK_PMALIVE2 368 369 #define ACLK_SATA0 369 370 #define ACLK_SATA1 370 371 #define ACLK_SATA2 371 372 #define CLK_RXOOB0 372 373 #define CLK_RXOOB1 373 374 #define CLK_RXOOB2 374 375 #define ACLK_USB3OTG2 375 376 #define SUSPEND_CLK_USB3OTG2 376 377 #define REF_CLK_USB3OTG2 377 378 #define CLK_UTMI_OTG2 378 379 #define CLK_PIPEPHY0_PIPE_G 379 380 #define CLK_PIPEPHY1_PIPE_G 380 381 #define CLK_PIPEPHY2_PIPE_G 381 382 #define CLK_PIPEPHY0_PIPE_ASIC_G 382 383 #define CLK_PIPEPHY1_PIPE_ASIC_G 383 384 #define CLK_PIPEPHY2_PIPE_ASIC_G 384 385 #define CLK_PIPEPHY2_PIPE_U3_G 385 386 #define CLK_PCIE1L2_PIPE 386 387 #define CLK_PCIE4L_PIPE 387 388 #define CLK_PCIE2L_PIPE 388 389 #define PCLK_PCIE_COMBO_PIPE_PHY0 389 390 #define PCLK_PCIE_COMBO_PIPE_PHY1 390 391 #define PCLK_PCIE_COMBO_PIPE_PHY2 391 392 #define PCLK_PCIE_COMBO_PIPE_PHY 392 393 #define HCLK_RGA3_1 393 394 #define ACLK_RGA3_1 394 395 #define CLK_RGA3_1_CORE 395 396 #define ACLK_RGA3_ROOT 396 397 #define HCLK_RGA3_ROOT 397 398 #define ACLK_RKVDEC_CCU 398 399 #define HCLK_RKVDEC0 399 400 #define ACLK_RKVDEC0 400 401 #define CLK_RKVDEC0_CA 401 402 #define CLK_RKVDEC0_HEVC_CA 402 403 #define CLK_RKVDEC0_CORE 403 404 #define HCLK_RKVDEC1 404 405 #define ACLK_RKVDEC1 405 406 #define CLK_RKVDEC1_CA 406 407 #define CLK_RKVDEC1_HEVC_CA 407 408 #define CLK_RKVDEC1_CORE 408 409 #define HCLK_SDIO 409 410 #define CCLK_SRC_SDIO 410 411 #define ACLK_USB_ROOT 411 412 #define HCLK_USB_ROOT 412 413 #define HCLK_HOST0 413 414 #define HCLK_HOST_ARB0 414 415 #define HCLK_HOST1 415 416 #define HCLK_HOST_ARB1 416 417 #define ACLK_USB3OTG0 417 418 #define SUSPEND_CLK_USB3OTG0 418 419 #define REF_CLK_USB3OTG0 419 420 #define ACLK_USB3OTG1 420 421 #define SUSPEND_CLK_USB3OTG1 421 422 #define REF_CLK_USB3OTG1 422 423 #define UTMI_OHCI_CLK48_HOST0 423 424 #define UTMI_OHCI_CLK48_HOST1 424 425 #define HCLK_IEP2P0 425 426 #define ACLK_IEP2P0 426 427 #define CLK_IEP2P0_CORE 427 428 #define ACLK_JPEG_ENCODER0 428 429 #define HCLK_JPEG_ENCODER0 429 430 #define ACLK_JPEG_ENCODER1 430 431 #define HCLK_JPEG_ENCODER1 431 432 #define ACLK_JPEG_ENCODER2 432 433 #define HCLK_JPEG_ENCODER2 433 434 #define ACLK_JPEG_ENCODER3 434 435 #define HCLK_JPEG_ENCODER3 435 436 #define ACLK_JPEG_DECODER 436 437 #define HCLK_JPEG_DECODER 437 438 #define HCLK_RGA2 438 439 #define ACLK_RGA2 439 440 #define CLK_RGA2_CORE 440 441 #define HCLK_RGA3_0 441 442 #define ACLK_RGA3_0 442 443 #define CLK_RGA3_0_CORE 443 444 #define ACLK_VDPU_ROOT 444 445 #define ACLK_VDPU_LOW_ROOT 445 446 #define HCLK_VDPU_ROOT 446 447 #define ACLK_JPEG_DECODER_ROOT 447 448 #define ACLK_VPU 448 449 #define HCLK_VPU 449 450 #define HCLK_RKVENC0_ROOT 450 451 #define ACLK_RKVENC0_ROOT 451 452 #define HCLK_RKVENC0 452 453 #define ACLK_RKVENC0 453 454 #define CLK_RKVENC0_CORE 454 455 #define HCLK_RKVENC1_ROOT 455 456 #define ACLK_RKVENC1_ROOT 456 457 #define HCLK_RKVENC1 457 458 #define ACLK_RKVENC1 458 459 #define CLK_RKVENC1_CORE 459 460 #define ICLK_CSIHOST01 460 461 #define ICLK_CSIHOST0 461 462 #define ICLK_CSIHOST1 462 463 #define PCLK_CSI_HOST_0 463 464 #define PCLK_CSI_HOST_1 464 465 #define PCLK_CSI_HOST_2 465 466 #define PCLK_CSI_HOST_3 466 467 #define PCLK_CSI_HOST_4 467 468 #define PCLK_CSI_HOST_5 468 469 #define ACLK_FISHEYE0 469 470 #define HCLK_FISHEYE0 470 471 #define CLK_FISHEYE0_CORE 471 472 #define ACLK_FISHEYE1 472 473 #define HCLK_FISHEYE1 473 474 #define CLK_FISHEYE1_CORE 474 475 #define CLK_ISP0_CORE 475 476 #define CLK_ISP0_CORE_MARVIN 476 477 #define CLK_ISP0_CORE_VICAP 477 478 #define ACLK_ISP0 478 479 #define HCLK_ISP0 479 480 #define ACLK_VI_ROOT 480 481 #define HCLK_VI_ROOT 481 482 #define PCLK_VI_ROOT 482 483 #define DCLK_VICAP 483 484 #define ACLK_VICAP 484 485 #define HCLK_VICAP 485 486 #define PCLK_DP0 486 487 #define PCLK_DP1 487 488 #define PCLK_S_DP0 488 489 #define PCLK_S_DP1 489 490 #define CLK_DP0 490 491 #define CLK_DP1 491 492 #define HCLK_HDCP_KEY0 492 493 #define ACLK_HDCP0 493 494 #define HCLK_HDCP0 494 495 #define PCLK_HDCP0 495 496 #define HCLK_I2S4_8CH 496 497 #define ACLK_TRNG0 497 498 #define PCLK_TRNG0 498 499 #define ACLK_VO0_ROOT 499 500 #define HCLK_VO0_ROOT 500 501 #define HCLK_VO0_S_ROOT 501 502 #define PCLK_VO0_ROOT 502 503 #define PCLK_VO0_S_ROOT 503 504 #define PCLK_VO0GRF 504 505 #define CLK_I2S4_8CH_TX_SRC 505 506 #define CLK_I2S4_8CH_TX_FRAC 506 507 #define MCLK_I2S4_8CH_TX 507 508 #define CLK_I2S4_8CH_TX 508 509 #define HCLK_I2S8_8CH 510 510 #define CLK_I2S8_8CH_TX_SRC 511 511 #define CLK_I2S8_8CH_TX_FRAC 512 512 #define MCLK_I2S8_8CH_TX 513 513 #define CLK_I2S8_8CH_TX 514 514 #define HCLK_SPDIF2_DP0 516 515 #define CLK_SPDIF2_DP0_SRC 517 516 #define CLK_SPDIF2_DP0_FRAC 518 517 #define MCLK_SPDIF2_DP0 519 518 #define CLK_SPDIF2_DP0 520 519 #define MCLK_SPDIF2 521 520 #define HCLK_SPDIF5_DP1 522 521 #define CLK_SPDIF5_DP1_SRC 523 522 #define CLK_SPDIF5_DP1_FRAC 524 523 #define MCLK_SPDIF5_DP1 525 524 #define CLK_SPDIF5_DP1 526 525 #define MCLK_SPDIF5 527 526 #define PCLK_EDP0 528 527 #define CLK_EDP0_24M 529 528 #define CLK_EDP0_200M 530 529 #define PCLK_EDP1 531 530 #define CLK_EDP1_24M 532 531 #define CLK_EDP1_200M 533 532 #define HCLK_HDCP_KEY1 534 533 #define ACLK_HDCP1 535 534 #define HCLK_HDCP1 536 535 #define PCLK_HDCP1 537 536 #define ACLK_HDMIRX 538 537 #define PCLK_HDMIRX 539 538 #define CLK_HDMIRX_REF 540 539 #define CLK_HDMIRX_AUD_SRC 541 540 #define CLK_HDMIRX_AUD_FRAC 542 541 #define CLK_HDMIRX_AUD 543 542 #define CLK_HDMIRX_AUD_P_MUX 544 543 #define PCLK_HDMITX0 545 544 #define CLK_HDMITX0_EARC 546 545 #define CLK_HDMITX0_REF 547 546 #define PCLK_HDMITX1 548 547 #define CLK_HDMITX1_EARC 549 548 #define CLK_HDMITX1_REF 550 549 #define CLK_HDMITRX_REFSRC 551 550 #define ACLK_TRNG1 552 551 #define PCLK_TRNG1 553 552 #define ACLK_HDCP1_ROOT 554 553 #define ACLK_HDMIRX_ROOT 555 554 #define HCLK_VO1_ROOT 556 555 #define HCLK_VO1_S_ROOT 557 556 #define PCLK_VO1_ROOT 558 557 #define PCLK_VO1_S_ROOT 559 558 #define PCLK_S_EDP0 560 559 #define PCLK_S_EDP1 561 560 #define PCLK_S_HDMIRX 562 561 #define HCLK_I2S10_8CH 563 562 #define CLK_I2S10_8CH_RX_SRC 564 563 #define CLK_I2S10_8CH_RX_FRAC 565 564 #define CLK_I2S10_8CH_RX 566 565 #define MCLK_I2S10_8CH_RX 567 566 #define HCLK_I2S7_8CH 568 567 #define CLK_I2S7_8CH_RX_SRC 569 568 #define CLK_I2S7_8CH_RX_FRAC 570 569 #define CLK_I2S7_8CH_RX 571 570 #define MCLK_I2S7_8CH_RX 572 571 #define HCLK_I2S9_8CH 574 572 #define CLK_I2S9_8CH_RX_SRC 575 573 #define CLK_I2S9_8CH_RX_FRAC 576 574 #define CLK_I2S9_8CH_RX 577 575 #define MCLK_I2S9_8CH_RX 578 576 #define CLK_I2S5_8CH_TX_SRC 579 577 #define CLK_I2S5_8CH_TX_FRAC 580 578 #define CLK_I2S5_8CH_TX 581 579 #define MCLK_I2S5_8CH_TX 582 580 #define HCLK_I2S5_8CH 584 581 #define CLK_I2S6_8CH_TX_SRC 585 582 #define CLK_I2S6_8CH_TX_FRAC 586 583 #define CLK_I2S6_8CH_TX 587 584 #define MCLK_I2S6_8CH_TX 588 585 #define CLK_I2S6_8CH_RX_SRC 589 586 #define CLK_I2S6_8CH_RX_FRAC 590 587 #define CLK_I2S6_8CH_RX 591 588 #define MCLK_I2S6_8CH_RX 592 589 #define I2S6_8CH_MCLKOUT 593 590 #define HCLK_I2S6_8CH 594 591 #define HCLK_SPDIF3 595 592 #define CLK_SPDIF3_SRC 596 593 #define CLK_SPDIF3_FRAC 597 594 #define CLK_SPDIF3 598 595 #define MCLK_SPDIF3 599 596 #define HCLK_SPDIF4 600 597 #define CLK_SPDIF4_SRC 601 598 #define CLK_SPDIF4_FRAC 602 599 #define CLK_SPDIF4 603 600 #define MCLK_SPDIF4 604 601 #define HCLK_SPDIFRX0 605 602 #define MCLK_SPDIFRX0 606 603 #define HCLK_SPDIFRX1 607 604 #define MCLK_SPDIFRX1 608 605 #define HCLK_SPDIFRX2 609 606 #define MCLK_SPDIFRX2 610 607 #define ACLK_VO1USB_TOP_ROOT 611 608 #define HCLK_VO1USB_TOP_ROOT 612 609 #define CLK_HDMIHDP0 613 610 #define CLK_HDMIHDP1 614 611 #define PCLK_HDPTX0 615 612 #define PCLK_HDPTX1 616 613 #define PCLK_USBDPPHY0 617 614 #define PCLK_USBDPPHY1 618 615 #define ACLK_VOP_ROOT 619 616 #define ACLK_VOP_LOW_ROOT 620 617 #define HCLK_VOP_ROOT 621 618 #define PCLK_VOP_ROOT 622 619 #define HCLK_VOP 623 620 #define ACLK_VOP 624 621 #define DCLK_VOP0_SRC 625 622 #define DCLK_VOP1_SRC 626 623 #define DCLK_VOP2_SRC 627 624 #define DCLK_VOP0 628 625 #define DCLK_VOP1 629 626 #define DCLK_VOP2 630 627 #define DCLK_VOP3 631 628 #define PCLK_DSIHOST0 632 629 #define PCLK_DSIHOST1 633 630 #define CLK_DSIHOST0 634 631 #define CLK_DSIHOST1 635 632 #define CLK_VOP_PMU 636 633 #define ACLK_VOP_DOBY 637 634 #define ACLK_VOP_SUB_SRC 638 635 #define CLK_USBDP_PHY0_IMMORTAL 639 636 #define CLK_USBDP_PHY1_IMMORTAL 640 637 #define CLK_PMU0 641 638 #define PCLK_PMU0 642 639 #define PCLK_PMU0IOC 643 640 #define PCLK_GPIO0 644 641 #define DBCLK_GPIO0 645 642 #define PCLK_I2C0 646 643 #define CLK_I2C0 647 644 #define HCLK_I2S1_8CH 648 645 #define CLK_I2S1_8CH_TX_SRC 649 646 #define CLK_I2S1_8CH_TX_FRAC 650 647 #define CLK_I2S1_8CH_TX 651 648 #define MCLK_I2S1_8CH_TX 652 649 #define CLK_I2S1_8CH_RX_SRC 653 650 #define CLK_I2S1_8CH_RX_FRAC 654 651 #define CLK_I2S1_8CH_RX 655 652 #define MCLK_I2S1_8CH_RX 656 653 #define I2S1_8CH_MCLKOUT 657 654 #define CLK_PMU1_50M_SRC 658 655 #define CLK_PMU1_100M_SRC 659 656 #define CLK_PMU1_200M_SRC 660 657 #define CLK_PMU1_300M_SRC 661 658 #define CLK_PMU1_400M_SRC 662 659 #define HCLK_PMU1_ROOT 663 660 #define PCLK_PMU1_ROOT 664 661 #define PCLK_PMU0_ROOT 665 662 #define HCLK_PMU_CM0_ROOT 666 663 #define PCLK_PMU1 667 664 #define CLK_DDR_FAIL_SAFE 668 665 #define CLK_PMU1 669 666 #define HCLK_PDM0 670 667 #define MCLK_PDM0 671 668 #define HCLK_VAD 672 669 #define FCLK_PMU_CM0_CORE 673 670 #define CLK_PMU_CM0_RTC 674 671 #define PCLK_PMU1_IOC 675 672 #define PCLK_PMU1PWM 676 673 #define CLK_PMU1PWM 677 674 #define CLK_PMU1PWM_CAPTURE 678 675 #define PCLK_PMU1TIMER 679 676 #define CLK_PMU1TIMER_ROOT 680 677 #define CLK_PMU1TIMER0 681 678 #define CLK_PMU1TIMER1 682 679 #define CLK_UART0_SRC 683 680 #define CLK_UART0_FRAC 684 681 #define CLK_UART0 685 682 #define SCLK_UART0 686 683 #define PCLK_UART0 687 684 #define PCLK_PMU1WDT 688 685 #define TCLK_PMU1WDT 689 686 #define CLK_CR_PARA 690 687 #define CLK_GMAC0 691 688 #define CLK_GMAC1 692 689 #define CLK_USB2PHY_HDPTXRXPHY_REF 693 690 #define CLK_USBDPPHY_MIPIDCPPHY_REF 694 691 #define CLK_REF_PIPE_PHY0_OSC_SRC 695 692 #define CLK_REF_PIPE_PHY1_OSC_SRC 696 693 #define CLK_REF_PIPE_PHY2_OSC_SRC 697 694 #define CLK_REF_PIPE_PHY0_PLL_SRC 698 695 #define CLK_REF_PIPE_PHY1_PLL_SRC 699 696 #define CLK_REF_PIPE_PHY2_PLL_SRC 700 697 #define CLK_REF_PIPE_PHY0 701 698 #define CLK_REF_PIPE_PHY1 702 699 #define CLK_REF_PIPE_PHY2 703 700 #define SCLK_SDIO_DRV 704 701 #define SCLK_SDIO_SAMPLE 705 702 #define SCLK_SDMMC_DRV 706 703 #define SCLK_SDMMC_SAMPLE 707 704 #define CLK_PCIE1L0_PIPE 708 705 #define CLK_PCIE1L1_PIPE 709 706 #define CLK_BIGCORE0_PVTM 710 707 #define CLK_CORE_BIGCORE0_PVTM 711 708 #define CLK_BIGCORE1_PVTM 712 709 #define CLK_CORE_BIGCORE1_PVTM 713 710 #define CLK_LITCORE_PVTM 714 711 #define CLK_CORE_LITCORE_PVTM 715 712 #define CLK_AUX16M_0 716 713 #define CLK_AUX16M_1 717 714 715 #define CLK_NR_CLKS (CLK_AUX16M_1 + 1) 716 717 /********Name=SOFTRST_CON01,Offset=0xA04********/ 718 #define SRST_A_TOP_BIU 19 719 #define SRST_P_TOP_BIU 20 720 #define SRST_P_CSIPHY0 22 721 #define SRST_CSIPHY0 23 722 #define SRST_P_CSIPHY1 24 723 #define SRST_CSIPHY1 25 724 #define SRST_A_TOP_M500_BIU 31 725 /********Name=SOFTRST_CON02,Offset=0xA08********/ 726 #define SRST_A_TOP_M400_BIU 32 727 #define SRST_A_TOP_S200_BIU 33 728 #define SRST_A_TOP_S400_BIU 34 729 #define SRST_A_TOP_M300_BIU 35 730 #define SRST_USBDP_COMBO_PHY0_INIT 40 731 #define SRST_USBDP_COMBO_PHY0_CMN 41 732 #define SRST_USBDP_COMBO_PHY0_LANE 42 733 #define SRST_USBDP_COMBO_PHY0_PCS 43 734 #define SRST_USBDP_COMBO_PHY1_INIT 47 735 /********Name=SOFTRST_CON03,Offset=0xA0C********/ 736 #define SRST_USBDP_COMBO_PHY1_CMN 48 737 #define SRST_USBDP_COMBO_PHY1_LANE 49 738 #define SRST_USBDP_COMBO_PHY1_PCS 50 739 #define SRST_DCPHY0 59 740 #define SRST_P_MIPI_DCPHY0 62 741 #define SRST_P_MIPI_DCPHY0_GRF 63 742 /********Name=SOFTRST_CON04,Offset=0xA10********/ 743 #define SRST_DCPHY1 64 744 #define SRST_P_MIPI_DCPHY1 67 745 #define SRST_P_MIPI_DCPHY1_GRF 68 746 #define SRST_P_APB2ASB_SLV_CDPHY 69 747 #define SRST_P_APB2ASB_SLV_CSIPHY 70 748 #define SRST_P_APB2ASB_SLV_VCCIO3_5 71 749 #define SRST_P_APB2ASB_SLV_VCCIO6 72 750 #define SRST_P_APB2ASB_SLV_EMMCIO 73 751 #define SRST_P_APB2ASB_SLV_IOC_TOP 74 752 #define SRST_P_APB2ASB_SLV_IOC_RIGHT 75 753 /********Name=SOFTRST_CON05,Offset=0xA14********/ 754 #define SRST_P_CRU 80 755 #define SRST_A_CHANNEL_SECURE2VO1USB 87 756 #define SRST_A_CHANNEL_SECURE2CENTER 88 757 #define SRST_H_CHANNEL_SECURE2VO1USB 94 758 #define SRST_H_CHANNEL_SECURE2CENTER 95 759 /********Name=SOFTRST_CON06,Offset=0xA18********/ 760 #define SRST_P_CHANNEL_SECURE2VO1USB 96 761 #define SRST_P_CHANNEL_SECURE2CENTER 97 762 /********Name=SOFTRST_CON07,Offset=0xA1C********/ 763 #define SRST_H_AUDIO_BIU 114 764 #define SRST_P_AUDIO_BIU 115 765 #define SRST_H_I2S0_8CH 116 766 #define SRST_M_I2S0_8CH_TX 119 767 #define SRST_M_I2S0_8CH_RX 122 768 #define SRST_P_ACDCDIG 123 769 #define SRST_H_I2S2_2CH 124 770 #define SRST_H_I2S3_2CH 125 771 /********Name=SOFTRST_CON08,Offset=0xA20********/ 772 #define SRST_M_I2S2_2CH 128 773 #define SRST_M_I2S3_2CH 131 774 #define SRST_DAC_ACDCDIG 132 775 #define SRST_H_SPDIF0 142 776 /********Name=SOFTRST_CON09,Offset=0xA24********/ 777 #define SRST_M_SPDIF0 145 778 #define SRST_H_SPDIF1 146 779 #define SRST_M_SPDIF1 149 780 #define SRST_H_PDM1 150 781 #define SRST_PDM1 151 782 /********Name=SOFTRST_CON10,Offset=0xA28********/ 783 #define SRST_A_BUS_BIU 161 784 #define SRST_P_BUS_BIU 162 785 #define SRST_A_GIC 163 786 #define SRST_A_GIC_DBG 164 787 #define SRST_A_DMAC0 165 788 #define SRST_A_DMAC1 166 789 #define SRST_A_DMAC2 167 790 #define SRST_P_I2C1 168 791 #define SRST_P_I2C2 169 792 #define SRST_P_I2C3 170 793 #define SRST_P_I2C4 171 794 #define SRST_P_I2C5 172 795 #define SRST_P_I2C6 173 796 #define SRST_P_I2C7 174 797 #define SRST_P_I2C8 175 798 /********Name=SOFTRST_CON11,Offset=0xA2C********/ 799 #define SRST_I2C1 176 800 #define SRST_I2C2 177 801 #define SRST_I2C3 178 802 #define SRST_I2C4 179 803 #define SRST_I2C5 180 804 #define SRST_I2C6 181 805 #define SRST_I2C7 182 806 #define SRST_I2C8 183 807 #define SRST_P_CAN0 184 808 #define SRST_CAN0 185 809 #define SRST_P_CAN1 186 810 #define SRST_CAN1 187 811 #define SRST_P_CAN2 188 812 #define SRST_CAN2 189 813 #define SRST_P_SARADC 190 814 /********Name=SOFTRST_CON12,Offset=0xA30********/ 815 #define SRST_P_TSADC 192 816 #define SRST_TSADC 193 817 #define SRST_P_UART1 194 818 #define SRST_P_UART2 195 819 #define SRST_P_UART3 196 820 #define SRST_P_UART4 197 821 #define SRST_P_UART5 198 822 #define SRST_P_UART6 199 823 #define SRST_P_UART7 200 824 #define SRST_P_UART8 201 825 #define SRST_P_UART9 202 826 #define SRST_S_UART1 205 827 /********Name=SOFTRST_CON13,Offset=0xA34********/ 828 #define SRST_S_UART2 208 829 #define SRST_S_UART3 211 830 #define SRST_S_UART4 214 831 #define SRST_S_UART5 217 832 #define SRST_S_UART6 220 833 #define SRST_S_UART7 223 834 /********Name=SOFTRST_CON14,Offset=0xA38********/ 835 #define SRST_S_UART8 226 836 #define SRST_S_UART9 229 837 #define SRST_P_SPI0 230 838 #define SRST_P_SPI1 231 839 #define SRST_P_SPI2 232 840 #define SRST_P_SPI3 233 841 #define SRST_P_SPI4 234 842 #define SRST_SPI0 235 843 #define SRST_SPI1 236 844 #define SRST_SPI2 237 845 #define SRST_SPI3 238 846 #define SRST_SPI4 239 847 /********Name=SOFTRST_CON15,Offset=0xA3C********/ 848 #define SRST_P_WDT0 240 849 #define SRST_T_WDT0 241 850 #define SRST_P_SYS_GRF 242 851 #define SRST_P_PWM1 243 852 #define SRST_PWM1 244 853 #define SRST_P_PWM2 246 854 #define SRST_PWM2 247 855 #define SRST_P_PWM3 249 856 #define SRST_PWM3 250 857 #define SRST_P_BUSTIMER0 252 858 #define SRST_P_BUSTIMER1 253 859 #define SRST_BUSTIMER0 255 860 /********Name=SOFTRST_CON16,Offset=0xA40********/ 861 #define SRST_BUSTIMER1 256 862 #define SRST_BUSTIMER2 257 863 #define SRST_BUSTIMER3 258 864 #define SRST_BUSTIMER4 259 865 #define SRST_BUSTIMER5 260 866 #define SRST_BUSTIMER6 261 867 #define SRST_BUSTIMER7 262 868 #define SRST_BUSTIMER8 263 869 #define SRST_BUSTIMER9 264 870 #define SRST_BUSTIMER10 265 871 #define SRST_BUSTIMER11 266 872 #define SRST_P_MAILBOX0 267 873 #define SRST_P_MAILBOX1 268 874 #define SRST_P_MAILBOX2 269 875 #define SRST_P_GPIO1 270 876 #define SRST_GPIO1 271 877 /********Name=SOFTRST_CON17,Offset=0xA44********/ 878 #define SRST_P_GPIO2 272 879 #define SRST_GPIO2 273 880 #define SRST_P_GPIO3 274 881 #define SRST_GPIO3 275 882 #define SRST_P_GPIO4 276 883 #define SRST_GPIO4 277 884 #define SRST_A_DECOM 278 885 #define SRST_P_DECOM 279 886 #define SRST_D_DECOM 280 887 #define SRST_P_TOP 281 888 #define SRST_A_GICADB_GIC2CORE_BUS 283 889 #define SRST_P_DFT2APB 284 890 #define SRST_P_APB2ASB_MST_TOP 285 891 #define SRST_P_APB2ASB_MST_CDPHY 286 892 #define SRST_P_APB2ASB_MST_BOT_RIGHT 287 893 /********Name=SOFTRST_CON18,Offset=0xA48********/ 894 #define SRST_P_APB2ASB_MST_IOC_TOP 288 895 #define SRST_P_APB2ASB_MST_IOC_RIGHT 289 896 #define SRST_P_APB2ASB_MST_CSIPHY 290 897 #define SRST_P_APB2ASB_MST_VCCIO3_5 291 898 #define SRST_P_APB2ASB_MST_VCCIO6 292 899 #define SRST_P_APB2ASB_MST_EMMCIO 293 900 #define SRST_A_SPINLOCK 294 901 #define SRST_P_OTPC_NS 297 902 #define SRST_OTPC_NS 298 903 #define SRST_OTPC_ARB 299 904 /********Name=SOFTRST_CON19,Offset=0xA4C********/ 905 #define SRST_P_BUSIOC 304 906 #define SRST_P_PMUCM0_INTMUX 308 907 #define SRST_P_DDRCM0_INTMUX 309 908 /********Name=SOFTRST_CON20,Offset=0xA50********/ 909 #define SRST_P_DDR_DFICTL_CH0 320 910 #define SRST_P_DDR_MON_CH0 321 911 #define SRST_P_DDR_STANDBY_CH0 322 912 #define SRST_P_DDR_UPCTL_CH0 323 913 #define SRST_TM_DDR_MON_CH0 324 914 #define SRST_P_DDR_GRF_CH01 325 915 #define SRST_DFI_CH0 326 916 #define SRST_SBR_CH0 327 917 #define SRST_DDR_UPCTL_CH0 328 918 #define SRST_DDR_DFICTL_CH0 329 919 #define SRST_DDR_MON_CH0 330 920 #define SRST_DDR_STANDBY_CH0 331 921 #define SRST_A_DDR_UPCTL_CH0 332 922 #define SRST_P_DDR_DFICTL_CH1 333 923 #define SRST_P_DDR_MON_CH1 334 924 #define SRST_P_DDR_STANDBY_CH1 335 925 /********Name=SOFTRST_CON21,Offset=0xA54********/ 926 #define SRST_P_DDR_UPCTL_CH1 336 927 #define SRST_TM_DDR_MON_CH1 337 928 #define SRST_DFI_CH1 338 929 #define SRST_SBR_CH1 339 930 #define SRST_DDR_UPCTL_CH1 340 931 #define SRST_DDR_DFICTL_CH1 341 932 #define SRST_DDR_MON_CH1 342 933 #define SRST_DDR_STANDBY_CH1 343 934 #define SRST_A_DDR_UPCTL_CH1 344 935 #define SRST_A_DDR01_MSCH0 349 936 #define SRST_A_DDR01_RS_MSCH0 350 937 #define SRST_A_DDR01_FRS_MSCH0 351 938 /********Name=SOFTRST_CON22,Offset=0xA58********/ 939 #define SRST_A_DDR01_SCRAMBLE0 352 940 #define SRST_A_DDR01_FRS_SCRAMBLE0 353 941 #define SRST_A_DDR01_MSCH1 354 942 #define SRST_A_DDR01_RS_MSCH1 355 943 #define SRST_A_DDR01_FRS_MSCH1 356 944 #define SRST_A_DDR01_SCRAMBLE1 357 945 #define SRST_A_DDR01_FRS_SCRAMBLE1 358 946 #define SRST_P_DDR01_MSCH0 359 947 #define SRST_P_DDR01_MSCH1 360 948 /********Name=SOFTRST_CON23,Offset=0xA5C********/ 949 #define SRST_P_DDR_DFICTL_CH2 368 950 #define SRST_P_DDR_MON_CH2 369 951 #define SRST_P_DDR_STANDBY_CH2 370 952 #define SRST_P_DDR_UPCTL_CH2 371 953 #define SRST_TM_DDR_MON_CH2 372 954 #define SRST_P_DDR_GRF_CH23 373 955 #define SRST_DFI_CH2 374 956 #define SRST_SBR_CH2 375 957 #define SRST_DDR_UPCTL_CH2 376 958 #define SRST_DDR_DFICTL_CH2 377 959 #define SRST_DDR_MON_CH2 378 960 #define SRST_DDR_STANDBY_CH2 379 961 #define SRST_A_DDR_UPCTL_CH2 380 962 #define SRST_P_DDR_DFICTL_CH3 381 963 #define SRST_P_DDR_MON_CH3 382 964 #define SRST_P_DDR_STANDBY_CH3 383 965 /********Name=SOFTRST_CON24,Offset=0xA60********/ 966 #define SRST_P_DDR_UPCTL_CH3 384 967 #define SRST_TM_DDR_MON_CH3 385 968 #define SRST_DFI_CH3 386 969 #define SRST_SBR_CH3 387 970 #define SRST_DDR_UPCTL_CH3 388 971 #define SRST_DDR_DFICTL_CH3 389 972 #define SRST_DDR_MON_CH3 390 973 #define SRST_DDR_STANDBY_CH3 391 974 #define SRST_A_DDR_UPCTL_CH3 392 975 #define SRST_A_DDR23_MSCH2 397 976 #define SRST_A_DDR23_RS_MSCH2 398 977 #define SRST_A_DDR23_FRS_MSCH2 399 978 /********Name=SOFTRST_CON25,Offset=0xA64********/ 979 #define SRST_A_DDR23_SCRAMBLE2 400 980 #define SRST_A_DDR23_FRS_SCRAMBLE2 401 981 #define SRST_A_DDR23_MSCH3 402 982 #define SRST_A_DDR23_RS_MSCH3 403 983 #define SRST_A_DDR23_FRS_MSCH3 404 984 #define SRST_A_DDR23_SCRAMBLE3 405 985 #define SRST_A_DDR23_FRS_SCRAMBLE3 406 986 #define SRST_P_DDR23_MSCH2 407 987 #define SRST_P_DDR23_MSCH3 408 988 /********Name=SOFTRST_CON26,Offset=0xA68********/ 989 #define SRST_ISP1 419 990 #define SRST_ISP1_VICAP 420 991 #define SRST_A_ISP1_BIU 422 992 #define SRST_H_ISP1_BIU 424 993 /********Name=SOFTRST_CON27,Offset=0xA6C********/ 994 #define SRST_A_RKNN1 432 995 #define SRST_A_RKNN1_BIU 433 996 #define SRST_H_RKNN1 434 997 #define SRST_H_RKNN1_BIU 435 998 /********Name=SOFTRST_CON28,Offset=0xA70********/ 999 #define SRST_A_RKNN2 448 1000 #define SRST_A_RKNN2_BIU 449 1001 #define SRST_H_RKNN2 450 1002 #define SRST_H_RKNN2_BIU 451 1003 /********Name=SOFTRST_CON29,Offset=0xA74********/ 1004 #define SRST_A_RKNN_DSU0 467 1005 #define SRST_P_NPUTOP_BIU 469 1006 #define SRST_P_NPU_TIMER 470 1007 #define SRST_NPUTIMER0 472 1008 #define SRST_NPUTIMER1 473 1009 #define SRST_P_NPU_WDT 474 1010 #define SRST_T_NPU_WDT 475 1011 #define SRST_P_NPU_PVTM 476 1012 #define SRST_P_NPU_GRF 477 1013 #define SRST_NPU_PVTM 478 1014 /********Name=SOFTRST_CON30,Offset=0xA78********/ 1015 #define SRST_NPU_PVTPLL 480 1016 #define SRST_H_NPU_CM0_BIU 482 1017 #define SRST_F_NPU_CM0_CORE 483 1018 #define SRST_T_NPU_CM0_JTAG 484 1019 #define SRST_A_RKNN0 486 1020 #define SRST_A_RKNN0_BIU 487 1021 #define SRST_H_RKNN0 488 1022 #define SRST_H_RKNN0_BIU 489 1023 /********Name=SOFTRST_CON31,Offset=0xA7C********/ 1024 #define SRST_H_NVM_BIU 498 1025 #define SRST_A_NVM_BIU 499 1026 #define SRST_H_EMMC 500 1027 #define SRST_A_EMMC 501 1028 #define SRST_C_EMMC 502 1029 #define SRST_B_EMMC 503 1030 #define SRST_T_EMMC 504 1031 #define SRST_S_SFC 505 1032 #define SRST_H_SFC 506 1033 #define SRST_H_SFC_XIP 507 1034 /********Name=SOFTRST_CON32,Offset=0xA80********/ 1035 #define SRST_P_GRF 513 1036 #define SRST_P_DEC_BIU 514 1037 #define SRST_P_PHP_BIU 517 1038 #define SRST_A_PCIE_GRIDGE 520 1039 #define SRST_A_PHP_BIU 521 1040 #define SRST_A_GMAC0 522 1041 #define SRST_A_GMAC1 523 1042 #define SRST_A_PCIE_BIU 524 1043 #define SRST_PCIE0_POWER_UP 525 1044 #define SRST_PCIE1_POWER_UP 526 1045 #define SRST_PCIE2_POWER_UP 527 1046 /********Name=SOFTRST_CON33,Offset=0xA84********/ 1047 #define SRST_PCIE3_POWER_UP 528 1048 #define SRST_PCIE4_POWER_UP 529 1049 #define SRST_P_PCIE0 540 1050 #define SRST_P_PCIE1 541 1051 #define SRST_P_PCIE2 542 1052 #define SRST_P_PCIE3 543 1053 /********Name=SOFTRST_CON34,Offset=0xA88********/ 1054 #define SRST_P_PCIE4 544 1055 #define SRST_A_PHP_GIC_ITS 550 1056 #define SRST_A_MMU_PCIE 551 1057 #define SRST_A_MMU_PHP 552 1058 #define SRST_A_MMU_BIU 553 1059 /********Name=SOFTRST_CON35,Offset=0xA8C********/ 1060 #define SRST_A_USB3OTG2 567 1061 /********Name=SOFTRST_CON37,Offset=0xA94********/ 1062 #define SRST_PMALIVE0 596 1063 #define SRST_PMALIVE1 597 1064 #define SRST_PMALIVE2 598 1065 #define SRST_A_SATA0 599 1066 #define SRST_A_SATA1 600 1067 #define SRST_A_SATA2 601 1068 #define SRST_RXOOB0 602 1069 #define SRST_RXOOB1 603 1070 #define SRST_RXOOB2 604 1071 #define SRST_ASIC0 605 1072 #define SRST_ASIC1 606 1073 #define SRST_ASIC2 607 1074 /********Name=SOFTRST_CON40,Offset=0xAA0********/ 1075 #define SRST_A_RKVDEC_CCU 642 1076 #define SRST_H_RKVDEC0 643 1077 #define SRST_A_RKVDEC0 644 1078 #define SRST_H_RKVDEC0_BIU 645 1079 #define SRST_A_RKVDEC0_BIU 646 1080 #define SRST_RKVDEC0_CA 647 1081 #define SRST_RKVDEC0_HEVC_CA 648 1082 #define SRST_RKVDEC0_CORE 649 1083 /********Name=SOFTRST_CON41,Offset=0xAA4********/ 1084 #define SRST_H_RKVDEC1 658 1085 #define SRST_A_RKVDEC1 659 1086 #define SRST_H_RKVDEC1_BIU 660 1087 #define SRST_A_RKVDEC1_BIU 661 1088 #define SRST_RKVDEC1_CA 662 1089 #define SRST_RKVDEC1_HEVC_CA 663 1090 #define SRST_RKVDEC1_CORE 664 1091 /********Name=SOFTRST_CON42,Offset=0xAA8********/ 1092 #define SRST_A_USB_BIU 674 1093 #define SRST_H_USB_BIU 675 1094 #define SRST_A_USB3OTG0 676 1095 #define SRST_A_USB3OTG1 679 1096 #define SRST_H_HOST0 682 1097 #define SRST_H_HOST_ARB0 683 1098 #define SRST_H_HOST1 684 1099 #define SRST_H_HOST_ARB1 685 1100 #define SRST_A_USB_GRF 686 1101 #define SRST_C_USB2P0_HOST0 687 1102 /********Name=SOFTRST_CON43,Offset=0xAAC********/ 1103 #define SRST_C_USB2P0_HOST1 688 1104 #define SRST_HOST_UTMI0 689 1105 #define SRST_HOST_UTMI1 690 1106 /********Name=SOFTRST_CON44,Offset=0xAB0********/ 1107 #define SRST_A_VDPU_BIU 708 1108 #define SRST_A_VDPU_LOW_BIU 709 1109 #define SRST_H_VDPU_BIU 710 1110 #define SRST_A_JPEG_DECODER_BIU 711 1111 #define SRST_A_VPU 712 1112 #define SRST_H_VPU 713 1113 #define SRST_A_JPEG_ENCODER0 714 1114 #define SRST_H_JPEG_ENCODER0 715 1115 #define SRST_A_JPEG_ENCODER1 716 1116 #define SRST_H_JPEG_ENCODER1 717 1117 #define SRST_A_JPEG_ENCODER2 718 1118 #define SRST_H_JPEG_ENCODER2 719 1119 /********Name=SOFTRST_CON45,Offset=0xAB4********/ 1120 #define SRST_A_JPEG_ENCODER3 720 1121 #define SRST_H_JPEG_ENCODER3 721 1122 #define SRST_A_JPEG_DECODER 722 1123 #define SRST_H_JPEG_DECODER 723 1124 #define SRST_H_IEP2P0 724 1125 #define SRST_A_IEP2P0 725 1126 #define SRST_IEP2P0_CORE 726 1127 #define SRST_H_RGA2 727 1128 #define SRST_A_RGA2 728 1129 #define SRST_RGA2_CORE 729 1130 #define SRST_H_RGA3_0 730 1131 #define SRST_A_RGA3_0 731 1132 #define SRST_RGA3_0_CORE 732 1133 /********Name=SOFTRST_CON47,Offset=0xABC********/ 1134 #define SRST_H_RKVENC0_BIU 754 1135 #define SRST_A_RKVENC0_BIU 755 1136 #define SRST_H_RKVENC0 756 1137 #define SRST_A_RKVENC0 757 1138 #define SRST_RKVENC0_CORE 758 1139 /********Name=SOFTRST_CON48,Offset=0xAC0********/ 1140 #define SRST_H_RKVENC1_BIU 770 1141 #define SRST_A_RKVENC1_BIU 771 1142 #define SRST_H_RKVENC1 772 1143 #define SRST_A_RKVENC1 773 1144 #define SRST_RKVENC1_CORE 774 1145 /********Name=SOFTRST_CON49,Offset=0xAC4********/ 1146 #define SRST_A_VI_BIU 787 1147 #define SRST_H_VI_BIU 788 1148 #define SRST_P_VI_BIU 789 1149 #define SRST_D_VICAP 790 1150 #define SRST_A_VICAP 791 1151 #define SRST_H_VICAP 792 1152 #define SRST_ISP0 794 1153 #define SRST_ISP0_VICAP 795 1154 /********Name=SOFTRST_CON50,Offset=0xAC8********/ 1155 #define SRST_FISHEYE0 800 1156 #define SRST_FISHEYE1 803 1157 #define SRST_P_CSI_HOST_0 804 1158 #define SRST_P_CSI_HOST_1 805 1159 #define SRST_P_CSI_HOST_2 806 1160 #define SRST_P_CSI_HOST_3 807 1161 #define SRST_P_CSI_HOST_4 808 1162 #define SRST_P_CSI_HOST_5 809 1163 /********Name=SOFTRST_CON51,Offset=0xACC********/ 1164 #define SRST_CSIHOST0_VICAP 820 1165 #define SRST_CSIHOST1_VICAP 821 1166 #define SRST_CSIHOST2_VICAP 822 1167 #define SRST_CSIHOST3_VICAP 823 1168 #define SRST_CSIHOST4_VICAP 824 1169 #define SRST_CSIHOST5_VICAP 825 1170 #define SRST_CIFIN 829 1171 /********Name=SOFTRST_CON52,Offset=0xAD0********/ 1172 #define SRST_A_VOP_BIU 836 1173 #define SRST_A_VOP_LOW_BIU 837 1174 #define SRST_H_VOP_BIU 838 1175 #define SRST_P_VOP_BIU 839 1176 #define SRST_H_VOP 840 1177 #define SRST_A_VOP 841 1178 #define SRST_D_VOP0 845 1179 #define SRST_D_VOP2HDMI_BRIDGE0 846 1180 #define SRST_D_VOP2HDMI_BRIDGE1 847 1181 /********Name=SOFTRST_CON53,Offset=0xAD4********/ 1182 #define SRST_D_VOP1 848 1183 #define SRST_D_VOP2 849 1184 #define SRST_D_VOP3 850 1185 #define SRST_P_VOPGRF 851 1186 #define SRST_P_DSIHOST0 852 1187 #define SRST_P_DSIHOST1 853 1188 #define SRST_DSIHOST0 854 1189 #define SRST_DSIHOST1 855 1190 #define SRST_VOP_PMU 856 1191 #define SRST_P_VOP_CHANNEL_BIU 857 1192 /********Name=SOFTRST_CON55,Offset=0xADC********/ 1193 #define SRST_H_VO0_BIU 885 1194 #define SRST_H_VO0_S_BIU 886 1195 #define SRST_P_VO0_BIU 887 1196 #define SRST_P_VO0_S_BIU 888 1197 #define SRST_A_HDCP0_BIU 889 1198 #define SRST_P_VO0GRF 890 1199 #define SRST_H_HDCP_KEY0 891 1200 #define SRST_A_HDCP0 892 1201 #define SRST_H_HDCP0 893 1202 #define SRST_HDCP0 895 1203 /********Name=SOFTRST_CON56,Offset=0xAE0********/ 1204 #define SRST_P_TRNG0 897 1205 #define SRST_DP0 904 1206 #define SRST_DP1 905 1207 #define SRST_H_I2S4_8CH 906 1208 #define SRST_M_I2S4_8CH_TX 909 1209 #define SRST_H_I2S8_8CH 910 1210 /********Name=SOFTRST_CON57,Offset=0xAE4********/ 1211 #define SRST_M_I2S8_8CH_TX 913 1212 #define SRST_H_SPDIF2_DP0 914 1213 #define SRST_M_SPDIF2_DP0 918 1214 #define SRST_H_SPDIF5_DP1 919 1215 #define SRST_M_SPDIF5_DP1 923 1216 /********Name=SOFTRST_CON59,Offset=0xAEC********/ 1217 #define SRST_A_HDCP1_BIU 950 1218 #define SRST_A_VO1_BIU 952 1219 #define SRST_H_VOP1_BIU 953 1220 #define SRST_H_VOP1_S_BIU 954 1221 #define SRST_P_VOP1_BIU 955 1222 #define SRST_P_VO1GRF 956 1223 #define SRST_P_VO1_S_BIU 957 1224 /********Name=SOFTRST_CON60,Offset=0xAF0********/ 1225 #define SRST_H_I2S7_8CH 960 1226 #define SRST_M_I2S7_8CH_RX 963 1227 #define SRST_H_HDCP_KEY1 964 1228 #define SRST_A_HDCP1 965 1229 #define SRST_H_HDCP1 966 1230 #define SRST_HDCP1 968 1231 #define SRST_P_TRNG1 970 1232 #define SRST_P_HDMITX0 971 1233 /********Name=SOFTRST_CON61,Offset=0xAF4********/ 1234 #define SRST_HDMITX0_REF 976 1235 #define SRST_P_HDMITX1 978 1236 #define SRST_HDMITX1_REF 983 1237 #define SRST_A_HDMIRX 985 1238 #define SRST_P_HDMIRX 986 1239 #define SRST_HDMIRX_REF 987 1240 /********Name=SOFTRST_CON62,Offset=0xAF8********/ 1241 #define SRST_P_EDP0 992 1242 #define SRST_EDP0_24M 993 1243 #define SRST_P_EDP1 995 1244 #define SRST_EDP1_24M 996 1245 #define SRST_M_I2S5_8CH_TX 1000 1246 #define SRST_H_I2S5_8CH 1004 1247 #define SRST_M_I2S6_8CH_TX 1007 1248 /********Name=SOFTRST_CON63,Offset=0xAFC********/ 1249 #define SRST_M_I2S6_8CH_RX 1010 1250 #define SRST_H_I2S6_8CH 1011 1251 #define SRST_H_SPDIF3 1012 1252 #define SRST_M_SPDIF3 1015 1253 #define SRST_H_SPDIF4 1016 1254 #define SRST_M_SPDIF4 1019 1255 #define SRST_H_SPDIFRX0 1020 1256 #define SRST_M_SPDIFRX0 1021 1257 #define SRST_H_SPDIFRX1 1022 1258 #define SRST_M_SPDIFRX1 1023 1259 /********Name=SOFTRST_CON64,Offset=0xB00********/ 1260 #define SRST_H_SPDIFRX2 1024 1261 #define SRST_M_SPDIFRX2 1025 1262 #define SRST_LINKSYM_HDMITXPHY0 1036 1263 #define SRST_LINKSYM_HDMITXPHY1 1037 1264 #define SRST_VO1_BRIDGE0 1038 1265 #define SRST_VO1_BRIDGE1 1039 1266 /********Name=SOFTRST_CON65,Offset=0xB04********/ 1267 #define SRST_H_I2S9_8CH 1040 1268 #define SRST_M_I2S9_8CH_RX 1043 1269 #define SRST_H_I2S10_8CH 1044 1270 #define SRST_M_I2S10_8CH_RX 1047 1271 #define SRST_P_S_HDMIRX 1048 1272 /********Name=SOFTRST_CON66,Offset=0xB08********/ 1273 #define SRST_GPU 1060 1274 #define SRST_SYS_GPU 1061 1275 #define SRST_A_S_GPU_BIU 1064 1276 #define SRST_A_M0_GPU_BIU 1065 1277 #define SRST_A_M1_GPU_BIU 1066 1278 #define SRST_A_M2_GPU_BIU 1067 1279 #define SRST_A_M3_GPU_BIU 1068 1280 #define SRST_P_GPU_BIU 1070 1281 #define SRST_P_GPU_PVTM 1071 1282 /********Name=SOFTRST_CON67,Offset=0xB0C********/ 1283 #define SRST_GPU_PVTM 1072 1284 #define SRST_P_GPU_GRF 1074 1285 #define SRST_GPU_PVTPLL 1075 1286 #define SRST_GPU_JTAG 1076 1287 /********Name=SOFTRST_CON68,Offset=0xB10********/ 1288 #define SRST_A_AV1_BIU 1089 1289 #define SRST_A_AV1 1090 1290 #define SRST_P_AV1_BIU 1092 1291 #define SRST_P_AV1 1093 1292 /********Name=SOFTRST_CON69,Offset=0xB14********/ 1293 #define SRST_A_DDR_BIU 1108 1294 #define SRST_A_DMA2DDR 1109 1295 #define SRST_A_DDR_SHAREMEM 1110 1296 #define SRST_A_DDR_SHAREMEM_BIU 1111 1297 #define SRST_A_CENTER_S200_BIU 1114 1298 #define SRST_A_CENTER_S400_BIU 1115 1299 #define SRST_H_AHB2APB 1116 1300 #define SRST_H_CENTER_BIU 1117 1301 #define SRST_F_DDR_CM0_CORE 1118 1302 /********Name=SOFTRST_CON70,Offset=0xB18********/ 1303 #define SRST_DDR_TIMER0 1120 1304 #define SRST_DDR_TIMER1 1121 1305 #define SRST_T_WDT_DDR 1122 1306 #define SRST_T_DDR_CM0_JTAG 1123 1307 #define SRST_P_CENTER_GRF 1125 1308 #define SRST_P_AHB2APB 1126 1309 #define SRST_P_WDT 1127 1310 #define SRST_P_TIMER 1128 1311 #define SRST_P_DMA2DDR 1129 1312 #define SRST_P_SHAREMEM 1130 1313 #define SRST_P_CENTER_BIU 1131 1314 #define SRST_P_CENTER_CHANNEL_BIU 1132 1315 /********Name=SOFTRST_CON72,Offset=0xB20********/ 1316 #define SRST_P_USBDPGRF0 1153 1317 #define SRST_P_USBDPPHY0 1154 1318 #define SRST_P_USBDPGRF1 1155 1319 #define SRST_P_USBDPPHY1 1156 1320 #define SRST_P_HDPTX0 1157 1321 #define SRST_P_HDPTX1 1158 1322 #define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159 1323 #define SRST_P_USB2PHY_U3_0_GRF0 1160 1324 #define SRST_P_USB2PHY_U3_1_GRF0 1161 1325 #define SRST_P_USB2PHY_U2_0_GRF0 1162 1326 #define SRST_P_USB2PHY_U2_1_GRF0 1163 1327 #define SRST_HDPTX0_ROPLL 1164 1328 #define SRST_HDPTX0_LCPLL 1165 1329 #define SRST_HDPTX0 1166 1330 #define SRST_HDPTX1_ROPLL 1167 1331 /********Name=SOFTRST_CON73,Offset=0xB24********/ 1332 #define SRST_HDPTX1_LCPLL 1168 1333 #define SRST_HDPTX1 1169 1334 #define SRST_HDPTX0_HDMIRXPHY_SET 1170 1335 #define SRST_USBDP_COMBO_PHY0 1171 1336 #define SRST_USBDP_COMBO_PHY0_LCPLL 1172 1337 #define SRST_USBDP_COMBO_PHY0_ROPLL 1173 1338 #define SRST_USBDP_COMBO_PHY0_PCS_HS 1174 1339 #define SRST_USBDP_COMBO_PHY1 1175 1340 #define SRST_USBDP_COMBO_PHY1_LCPLL 1176 1341 #define SRST_USBDP_COMBO_PHY1_ROPLL 1177 1342 #define SRST_USBDP_COMBO_PHY1_PCS_HS 1178 1343 #define SRST_HDMIHDP0 1180 1344 #define SRST_HDMIHDP1 1181 1345 /********Name=SOFTRST_CON74,Offset=0xB28********/ 1346 #define SRST_A_VO1USB_TOP_BIU 1185 1347 #define SRST_H_VO1USB_TOP_BIU 1187 1348 /********Name=SOFTRST_CON75,Offset=0xB2C********/ 1349 #define SRST_H_SDIO_BIU 1201 1350 #define SRST_H_SDIO 1202 1351 #define SRST_SDIO 1203 1352 /********Name=SOFTRST_CON76,Offset=0xB30********/ 1353 #define SRST_H_RGA3_BIU 1218 1354 #define SRST_A_RGA3_BIU 1219 1355 #define SRST_H_RGA3_1 1220 1356 #define SRST_A_RGA3_1 1221 1357 #define SRST_RGA3_1_CORE 1222 1358 /********Name=SOFTRST_CON77,Offset=0xB34********/ 1359 #define SRST_REF_PIPE_PHY0 1238 1360 #define SRST_REF_PIPE_PHY1 1239 1361 #define SRST_REF_PIPE_PHY2 1240 1362 1363 /********Name=PHPTOPSOFTRST_CON0,Offset=0x8A00********/ 1364 #define SRST_P_PHPTOP_CRU 131073 1365 #define SRST_P_PCIE2_GRF0 131074 1366 #define SRST_P_PCIE2_GRF1 131075 1367 #define SRST_P_PCIE2_GRF2 131076 1368 #define SRST_P_PCIE2_PHY0 131077 1369 #define SRST_P_PCIE2_PHY1 131078 1370 #define SRST_P_PCIE2_PHY2 131079 1371 #define SRST_P_PCIE3_PHY 131080 1372 #define SRST_P_APB2ASB_SLV_CHIP_TOP 131081 1373 #define SRST_PCIE30_PHY 131082 1374 1375 /********Name=PMU1SOFTRST_CON00,Offset=0x30A00********/ 1376 #define SRST_H_PMU1_BIU 786442 1377 #define SRST_P_PMU1_BIU 786443 1378 #define SRST_H_PMU_CM0_BIU 786444 1379 #define SRST_F_PMU_CM0_CORE 786445 1380 #define SRST_T_PMU1_CM0_JTAG 786446 1381 1382 /********Name=PMU1SOFTRST_CON01,Offset=0x30A04********/ 1383 #define SRST_DDR_FAIL_SAFE 786449 1384 #define SRST_P_CRU_PMU1 786450 1385 #define SRST_P_PMU1_GRF 786452 1386 #define SRST_P_PMU1_IOC 786453 1387 #define SRST_P_PMU1WDT 786454 1388 #define SRST_T_PMU1WDT 786455 1389 #define SRST_P_PMU1TIMER 786456 1390 #define SRST_PMU1TIMER0 786458 1391 #define SRST_PMU1TIMER1 786459 1392 #define SRST_P_PMU1PWM 786460 1393 #define SRST_PMU1PWM 786461 1394 1395 /********Name=PMU1SOFTRST_CON02,Offset=0x30A08********/ 1396 #define SRST_P_I2C0 786465 1397 #define SRST_I2C0 786466 1398 #define SRST_S_UART0 786469 1399 #define SRST_P_UART0 786470 1400 #define SRST_H_I2S1_8CH 786471 1401 #define SRST_M_I2S1_8CH_TX 786474 1402 #define SRST_M_I2S1_8CH_RX 786477 1403 #define SRST_H_PDM0 786478 1404 #define SRST_PDM0 786479 1405 1406 /********Name=PMU1SOFTRST_CON03,Offset=0x30A0C********/ 1407 #define SRST_H_VAD 786480 1408 #define SRST_HDPTX0_INIT 786491 1409 #define SRST_HDPTX0_CMN 786492 1410 #define SRST_HDPTX0_LANE 786493 1411 #define SRST_HDPTX1_INIT 786495 1412 1413 /********Name=PMU1SOFTRST_CON04,Offset=0x30A10********/ 1414 #define SRST_HDPTX1_CMN 786496 1415 #define SRST_HDPTX1_LANE 786497 1416 #define SRST_M_MIPI_DCPHY0 786499 1417 #define SRST_S_MIPI_DCPHY0 786500 1418 #define SRST_M_MIPI_DCPHY1 786501 1419 #define SRST_S_MIPI_DCPHY1 786502 1420 #define SRST_OTGPHY_U3_0 786503 1421 #define SRST_OTGPHY_U3_1 786504 1422 #define SRST_OTGPHY_U2_0 786505 1423 #define SRST_OTGPHY_U2_1 786506 1424 1425 /********Name=PMU1SOFTRST_CON05,Offset=0x30A14********/ 1426 #define SRST_P_PMU0GRF 786515 1427 #define SRST_P_PMU0IOC 786516 1428 #define SRST_P_GPIO0 786517 1429 #define SRST_GPIO0 786518 1430 1431 /* scmi-clocks indices */ 1432 1433 #define SCMI_CLK_CPUL 0 1434 #define SCMI_CLK_DSU 1 1435 #define SCMI_CLK_CPUB01 2 1436 #define SCMI_CLK_CPUB23 3 1437 #define SCMI_CLK_DDR 4 1438 #define SCMI_CLK_GPU 5 1439 #define SCMI_CLK_NPU 6 1440 #define SCMI_CLK_SBUS 7 1441 #define SCMI_PCLK_SBUS 8 1442 #define SCMI_CCLK_SD 9 1443 #define SCMI_DCLK_SD 10 1444 #define SCMI_ACLK_SECURE_NS 11 1445 #define SCMI_HCLK_SECURE_NS 12 1446 #define SCMI_TCLK_WDT 13 1447 #define SCMI_KEYLADDER_CORE 14 1448 #define SCMI_KEYLADDER_RNG 15 1449 #define SCMI_ACLK_SECURE_S 16 1450 #define SCMI_HCLK_SECURE_S 17 1451 #define SCMI_PCLK_SECURE_S 18 1452 #define SCMI_CRYPTO_RNG 19 1453 #define SCMI_CRYPTO_CORE 20 1454 #define SCMI_CRYPTO_PKA 21 1455 #define SCMI_SPLL 22 1456 #define SCMI_HCLK_SD 23 1457 1458 /********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/ 1459 #define SRST_A_SECURE_NS_BIU 10 1460 #define SRST_H_SECURE_NS_BIU 11 1461 #define SRST_A_SECURE_S_BIU 12 1462 #define SRST_H_SECURE_S_BIU 13 1463 #define SRST_P_SECURE_S_BIU 14 1464 #define SRST_CRYPTO_CORE 15 1465 /********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/ 1466 #define SRST_CRYPTO_PKA 16 1467 #define SRST_CRYPTO_RNG 17 1468 #define SRST_A_CRYPTO 18 1469 #define SRST_H_CRYPTO 19 1470 #define SRST_KEYLADDER_CORE 25 1471 #define SRST_KEYLADDER_RNG 26 1472 #define SRST_A_KEYLADDER 27 1473 #define SRST_H_KEYLADDER 28 1474 #define SRST_P_OTPC_S 29 1475 #define SRST_OTPC_S 30 1476 #define SRST_WDT_S 31 1477 /********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/ 1478 #define SRST_T_WDT_S 32 1479 #define SRST_H_BOOTROM 33 1480 #define SRST_A_DCF 34 1481 #define SRST_P_DCF 35 1482 #define SRST_H_BOOTROM_NS 37 1483 #define SRST_P_KEYLADDER 46 1484 #define SRST_H_TRNG_S 47 1485 /********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/ 1486 #define SRST_H_TRNG_NS 48 1487 #define SRST_D_SDMMC_BUFFER 49 1488 #define SRST_H_SDMMC 50 1489 #define SRST_H_SDMMC_BUFFER 51 1490 #define SRST_SDMMC 52 1491 #define SRST_P_TRNG_CHK 53 1492 #define SRST_TRNG_S 54 1493 1494 #endif 1495