Searched refs:CLK_REF_PIPE_PHY0 (Results 1 – 6 of 6) sorted by relevance
1431 case CLK_REF_PIPE_PHY0: in rk3588_pciephy_get_rate()1474 case CLK_REF_PIPE_PHY0: in rk3588_pciephy_set_rate()1643 case CLK_REF_PIPE_PHY0: in rk3588_clk_get_rate()1792 case CLK_REF_PIPE_PHY0: in rk3588_clk_set_rate()
695 #define CLK_REF_PIPE_PHY0 701 macro
697 #define CLK_REF_PIPE_PHY0 701 macro
2293 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;2295 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2123 MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT,
6709 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,6712 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;