Searched refs:CLK_ENABLE (Results 1 – 8 of 8) sorted by relevance
66 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ macro157 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | in sh_mmcif_boot_do_read()190 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | in sh_mmcif_boot_init()
117 #define CLK_ENABLE (1 << 8) macro
104 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()116 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()123 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
89 #define CLK_ENABLE (1 << 24) macro
182 ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL)); in sh_sdhi_clock_control()203 CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); in sh_sdhi_clock_control()216 CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); in sh_sdhi_sync_reset()
40 #define CLK_ENABLE BIT(0) macro420 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE; in mipid02_configure_clk_lane()
486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()533 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
967 DUMPREG(CLK_ENABLE); in vpe_dump_regs()