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Searched refs:CCCR (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/pxa/
H A Dclk-pxa25x.c124 unsigned long cccr = readl(CCCR); in clk_pxa25x_memory_get_rate()
228 unsigned long cccr = readl(CCCR); in clk_pxa25x_run_get_rate()
239 unsigned long clkcfg, cccr = readl(CCCR); in clk_pxa25x_cpll_get_rate()
271 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa25x_cpll_set_rate()
H A Dclk-pxa27x.c263 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa27x_cpll_set_rate()
275 unsigned long cccr = readl(CCCR); in clk_pxa27x_lcd_base_get_rate()
418 unsigned long cccr = readl(CCCR); in clk_pxa27x_memory_get_rate()
437 unsigned long cccr = readl(CCCR); in clk_pxa27x_memory_get_parent()
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dsleep.S69 ldr r6, =CCCR
72 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
112 ldr r6, =CCCR
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/include/mach/
H A Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ macro
/OK3568_Linux_fs/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c230 writel(CONFIG_SYS_CCCR, CCCR); in pxa_clock_setup()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h1040 #define CCCR 0x41300000 /* Core Clock Configuration Register */ macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/nxp/
H A DREADME_MLAN281 And there is a limitation for function 0 write, only vendor specific CCCR
3822 is a limitation for function 0 write, only vendor specific CCCR registers