1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Taken from pxa-regs.h by Russell King 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Nicolas Pitre 8*4882a593Smuzhiyun * Copyright: MontaVista Software Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __PXA2XX_REGS_H 12*4882a593Smuzhiyun #define __PXA2XX_REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <mach/hardware.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Power Manager 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ 21*4882a593Smuzhiyun #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ 22*4882a593Smuzhiyun #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ 23*4882a593Smuzhiyun #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ 24*4882a593Smuzhiyun #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ 25*4882a593Smuzhiyun #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ 26*4882a593Smuzhiyun #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ 27*4882a593Smuzhiyun #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ 28*4882a593Smuzhiyun #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ 29*4882a593Smuzhiyun #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ 30*4882a593Smuzhiyun #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ 31*4882a593Smuzhiyun #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ 32*4882a593Smuzhiyun #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ 35*4882a593Smuzhiyun #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ 36*4882a593Smuzhiyun #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ 37*4882a593Smuzhiyun #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ 38*4882a593Smuzhiyun #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ 39*4882a593Smuzhiyun #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ 40*4882a593Smuzhiyun #define PCMD(x) __REG2(0x40F00080, (x)<<2) 41*4882a593Smuzhiyun #define PCMD0 __REG(0x40F00080 + 0 * 4) 42*4882a593Smuzhiyun #define PCMD1 __REG(0x40F00080 + 1 * 4) 43*4882a593Smuzhiyun #define PCMD2 __REG(0x40F00080 + 2 * 4) 44*4882a593Smuzhiyun #define PCMD3 __REG(0x40F00080 + 3 * 4) 45*4882a593Smuzhiyun #define PCMD4 __REG(0x40F00080 + 4 * 4) 46*4882a593Smuzhiyun #define PCMD5 __REG(0x40F00080 + 5 * 4) 47*4882a593Smuzhiyun #define PCMD6 __REG(0x40F00080 + 6 * 4) 48*4882a593Smuzhiyun #define PCMD7 __REG(0x40F00080 + 7 * 4) 49*4882a593Smuzhiyun #define PCMD8 __REG(0x40F00080 + 8 * 4) 50*4882a593Smuzhiyun #define PCMD9 __REG(0x40F00080 + 9 * 4) 51*4882a593Smuzhiyun #define PCMD10 __REG(0x40F00080 + 10 * 4) 52*4882a593Smuzhiyun #define PCMD11 __REG(0x40F00080 + 11 * 4) 53*4882a593Smuzhiyun #define PCMD12 __REG(0x40F00080 + 12 * 4) 54*4882a593Smuzhiyun #define PCMD13 __REG(0x40F00080 + 13 * 4) 55*4882a593Smuzhiyun #define PCMD14 __REG(0x40F00080 + 14 * 4) 56*4882a593Smuzhiyun #define PCMD15 __REG(0x40F00080 + 15 * 4) 57*4882a593Smuzhiyun #define PCMD16 __REG(0x40F00080 + 16 * 4) 58*4882a593Smuzhiyun #define PCMD17 __REG(0x40F00080 + 17 * 4) 59*4882a593Smuzhiyun #define PCMD18 __REG(0x40F00080 + 18 * 4) 60*4882a593Smuzhiyun #define PCMD19 __REG(0x40F00080 + 19 * 4) 61*4882a593Smuzhiyun #define PCMD20 __REG(0x40F00080 + 20 * 4) 62*4882a593Smuzhiyun #define PCMD21 __REG(0x40F00080 + 21 * 4) 63*4882a593Smuzhiyun #define PCMD22 __REG(0x40F00080 + 22 * 4) 64*4882a593Smuzhiyun #define PCMD23 __REG(0x40F00080 + 23 * 4) 65*4882a593Smuzhiyun #define PCMD24 __REG(0x40F00080 + 24 * 4) 66*4882a593Smuzhiyun #define PCMD25 __REG(0x40F00080 + 25 * 4) 67*4882a593Smuzhiyun #define PCMD26 __REG(0x40F00080 + 26 * 4) 68*4882a593Smuzhiyun #define PCMD27 __REG(0x40F00080 + 27 * 4) 69*4882a593Smuzhiyun #define PCMD28 __REG(0x40F00080 + 28 * 4) 70*4882a593Smuzhiyun #define PCMD29 __REG(0x40F00080 + 29 * 4) 71*4882a593Smuzhiyun #define PCMD30 __REG(0x40F00080 + 30 * 4) 72*4882a593Smuzhiyun #define PCMD31 __REG(0x40F00080 + 31 * 4) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define PCMD_MBC (1<<12) 75*4882a593Smuzhiyun #define PCMD_DCE (1<<11) 76*4882a593Smuzhiyun #define PCMD_LC (1<<10) 77*4882a593Smuzhiyun /* FIXME: PCMD_SQC need be checked. */ 78*4882a593Smuzhiyun #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, 79*4882a593Smuzhiyun bit 9 should be 0 all day. */ 80*4882a593Smuzhiyun #define PVCR_VCSA (0x1<<14) 81*4882a593Smuzhiyun #define PVCR_CommandDelay (0xf80) 82*4882a593Smuzhiyun #define PCFR_PI2C_EN (0x1 << 6) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ 85*4882a593Smuzhiyun #define PSSR_RDH (1 << 5) /* Read Disable Hold */ 86*4882a593Smuzhiyun #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ 87*4882a593Smuzhiyun #define PSSR_STS (1 << 3) /* Standby Mode Status */ 88*4882a593Smuzhiyun #define PSSR_VFS (1 << 2) /* VDD Fault Status */ 89*4882a593Smuzhiyun #define PSSR_BFS (1 << 1) /* Battery Fault Status */ 90*4882a593Smuzhiyun #define PSSR_SSS (1 << 0) /* Software Sleep Status */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define PCFR_RO (1 << 15) /* RDH Override */ 95*4882a593Smuzhiyun #define PCFR_PO (1 << 14) /* PH Override */ 96*4882a593Smuzhiyun #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ 97*4882a593Smuzhiyun #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ 98*4882a593Smuzhiyun #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ 99*4882a593Smuzhiyun #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ 100*4882a593Smuzhiyun #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ 101*4882a593Smuzhiyun #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ 102*4882a593Smuzhiyun #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ 103*4882a593Smuzhiyun #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ 104*4882a593Smuzhiyun #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ 105*4882a593Smuzhiyun #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define RCSR_GPR (1 << 3) /* GPIO Reset */ 108*4882a593Smuzhiyun #define RCSR_SMR (1 << 2) /* Sleep Mode */ 109*4882a593Smuzhiyun #define RCSR_WDR (1 << 1) /* Watchdog Reset */ 110*4882a593Smuzhiyun #define RCSR_HWR (1 << 0) /* Hardware Reset */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ 113*4882a593Smuzhiyun #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ 114*4882a593Smuzhiyun #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ 115*4882a593Smuzhiyun #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ 116*4882a593Smuzhiyun #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ 117*4882a593Smuzhiyun #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ 118*4882a593Smuzhiyun #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ 119*4882a593Smuzhiyun #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ 120*4882a593Smuzhiyun #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ 121*4882a593Smuzhiyun #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ 122*4882a593Smuzhiyun #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ 123*4882a593Smuzhiyun #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ 124*4882a593Smuzhiyun #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ 125*4882a593Smuzhiyun #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ 126*4882a593Smuzhiyun #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ 127*4882a593Smuzhiyun #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ 128*4882a593Smuzhiyun #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 129*4882a593Smuzhiyun #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * PXA2xx specific Core clock definitions 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ 135*4882a593Smuzhiyun #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ 136*4882a593Smuzhiyun #define CKEN io_p2v(0x41300004) /* Clock Enable Register */ 137*4882a593Smuzhiyun #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ 140*4882a593Smuzhiyun #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ 141*4882a593Smuzhiyun #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define CCCR_CPDIS_BIT (31) 144*4882a593Smuzhiyun #define CCCR_PPDIS_BIT (30) 145*4882a593Smuzhiyun #define CCCR_LCD_26_BIT (27) 146*4882a593Smuzhiyun #define CCCR_A_BIT (25) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define CCSR_N2_MASK CCCR_N_MASK 149*4882a593Smuzhiyun #define CCSR_M_MASK CCCR_M_MASK 150*4882a593Smuzhiyun #define CCSR_L_MASK CCCR_L_MASK 151*4882a593Smuzhiyun #define CCSR_N2_SHIFT 7 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ 154*4882a593Smuzhiyun #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ 155*4882a593Smuzhiyun #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ 156*4882a593Smuzhiyun #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ 157*4882a593Smuzhiyun #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ 158*4882a593Smuzhiyun #define CKEN_IM (20) /* Internal Memory Clock Enable */ 159*4882a593Smuzhiyun #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ 160*4882a593Smuzhiyun #define CKEN_USIM (18) /* USIM Unit Clock Enable */ 161*4882a593Smuzhiyun #define CKEN_MSL (17) /* MSL Unit Clock Enable */ 162*4882a593Smuzhiyun #define CKEN_LCD (16) /* LCD Unit Clock Enable */ 163*4882a593Smuzhiyun #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ 164*4882a593Smuzhiyun #define CKEN_I2C (14) /* I2C Unit Clock Enable */ 165*4882a593Smuzhiyun #define CKEN_FICP (13) /* FICP Unit Clock Enable */ 166*4882a593Smuzhiyun #define CKEN_MMC (12) /* MMC Unit Clock Enable */ 167*4882a593Smuzhiyun #define CKEN_USB (11) /* USB Unit Clock Enable */ 168*4882a593Smuzhiyun #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ 169*4882a593Smuzhiyun #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ 170*4882a593Smuzhiyun #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ 171*4882a593Smuzhiyun #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ 172*4882a593Smuzhiyun #define CKEN_I2S (8) /* I2S Unit Clock Enable */ 173*4882a593Smuzhiyun #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ 174*4882a593Smuzhiyun #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ 175*4882a593Smuzhiyun #define CKEN_STUART (5) /* STUART Unit Clock Enable */ 176*4882a593Smuzhiyun #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ 177*4882a593Smuzhiyun #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ 178*4882a593Smuzhiyun #define CKEN_SSP (3) /* SSP Unit Clock Enable */ 179*4882a593Smuzhiyun #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ 180*4882a593Smuzhiyun #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ 181*4882a593Smuzhiyun #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ 182*4882a593Smuzhiyun #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 185*4882a593Smuzhiyun #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* PWRMODE register M field values */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define PWRMODE_IDLE 0x1 190*4882a593Smuzhiyun #define PWRMODE_STANDBY 0x2 191*4882a593Smuzhiyun #define PWRMODE_SLEEP 0x3 192*4882a593Smuzhiyun #define PWRMODE_DEEPSLEEP 0x7 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #endif 195