Searched refs:BUS_ACLK_HZ (Results 1 – 4 of 4) sorted by relevance
144 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()145 assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()147 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; in rkclk_init()148 assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7); in rkclk_init()150 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()151 assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3); in rkclk_init()
1278 rk3308_bus_set_clk(priv, ACLK_BUS, BUS_ACLK_HZ); in rk3308_clk_init()
19 #define BUS_ACLK_HZ 148500000 macro
19 #define BUS_ACLK_HZ 200000000 macro