"f6457ce5789b885706a2877edb70b5f8e61cf075" (history) in projects: rk3399_rockchip-uboot

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Searched hist:f6457ce5789b885706a2877edb70b5f8e61cf075 (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-sunxi/dram_timings/
H A D	ddr3_1333.c	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`
H A D	Makefile	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A D	dram_sunxi_dw.h	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A D	dram_sunxi_dw.c	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`
H A D	Makefile	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`
H A D	Kconfig	`f6457ce5789b885706a2877edb70b5f8e61cf075 Sat Jun 03 09:10:18 UTC 2017 Icenowy Zheng <icenowy@aosc.xyz> sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>`