Searched hist:ee5b26fd0058d5e696cdf83bf389351eab296bf7 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/allwinner/sun50i_h616/ |
| H A D | sunxi_h616_dtb.c | ee5b26fd0058d5e696cdf83bf389351eab296bf7 Wed May 01 13:05:24 UTC 2024 Andre Przywara <andre.przywara@arm.com> feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| H A D | platform.mk | ee5b26fd0058d5e696cdf83bf389351eab296bf7 Wed May 01 13:05:24 UTC 2024 Andre Przywara <andre.przywara@arm.com> feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_prepare_dtb.c | ee5b26fd0058d5e696cdf83bf389351eab296bf7 Wed May 01 13:05:24 UTC 2024 Andre Przywara <andre.przywara@arm.com> feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/plat/allwinner/common/include/ |
| H A D | sunxi_private.h | ee5b26fd0058d5e696cdf83bf389351eab296bf7 Wed May 01 13:05:24 UTC 2024 Andre Przywara <andre.przywara@arm.com> feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|