Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: ad

Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model

show more ...

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cac

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.

Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.

The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.

Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(al

Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(allwinner): choose PSCI states to avoid translation
feat(fdt): add the ability to supply idle state information
fix(allwinner): improve DTB patching error handling
refactor(allwinner): patch the DTB after setting up PSCI
refactor(allwinner): move DTB change code into allwinner/common

show more ...

feat(allwinner): provide CPU idle states to the rich OS

When using SCPI as the PSCI backend, firmware can wake up the CPUs and
cluster from sleep, so CPU idle states are available for the rich OS to

feat(allwinner): provide CPU idle states to the rich OS

When using SCPI as the PSCI backend, firmware can wake up the CPUs and
cluster from sleep, so CPU idle states are available for the rich OS to
use. In that case, advertise them to the rich OS via the DTB.

Change-Id: I718ef6ef41212fe5213b11b4799613adbbe6e0eb
Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

refactor(allwinner): move DTB change code into allwinner/common

So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoC

refactor(allwinner): move DTB change code into allwinner/common

So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoCs to modify the DTB as well, without duplicating code,
move the DTB change routines into Allwinner common code, and generalise
the current code to allow other modifications.

No functional change intended.

Change-Id: I080ea07b6470367f3c2573a4368f8ef5196d411c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping

show more ...

allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-

allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.

Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge "allwinner: Allow conditional compilation of SCPI and native PSCI ops" into integration

Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allw

Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
allwinner: Separate code to power off self and other CPUs

show more ...

allwinner: Allow conditional compilation of SCPI and native PSCI ops

Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or bo

allwinner: Allow conditional compilation of SCPI and native PSCI ops

Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or both of them.

If one version is not compiled in, some stub functions make sure the
common code still compiles and makes the right decisions.

By default both version are enabled (as before), but one of them can be
disabled on the make command line, or via a platform specific Makefile.

Change-Id: I0c019d8700c0208365eacf57809fb8bc608eb9c0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

allwinner: Split native and SCPI-based PSCI implementations

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out

allwinner: Split native and SCPI-based PSCI implementations

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out to be
a good decision, as some newer SoCs omit the ARISC, and thus cannot run
SCP firmware.

However, keeping the two implementations in one file makes things
unnecessarily messy. First, it is difficult to compile out the
SCPI-based implementation where it is not applicable. Second the check
is done in each callback, while scpi_available is only updated at boot.
This makes the individual callbacks unnecessarily complicated.

It is cleaner to provide two entirely separate implementations in two
separate files. The native implementation does not support any kind of
CPU suspend, so its callbacks are greatly simplified. One function,
sunxi_validate_ns_entrypoint, is shared between the two implementations.

Finally, the logic for choosing between implementations is kept in a
third file, to provide for platforms where only one implementation is
applicable and the other is compiled out.

Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.

allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.

Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

Merge changes from topic "allwinner_pmic" into integration

* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a6

Merge changes from topic "allwinner_pmic" into integration

* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a64: power: Remove obsolete register check
allwinner: a64: power: Remove duplicate DT check
allwinner: Build PMIC bus drivers only in BL31
allwinner: a64: power: Make sunxi_turn_off_soc static
allwinner: Merge duplicate code in sunxi_power_down
allwinner: Clean up PMIC-related error handling
allwinner: Synchronize PMIC enumerations
allwinner: Enable clock before resetting I2C/RSB

show more ...

allwinner: Merge duplicate code in sunxi_power_down

The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matche

allwinner: Merge duplicate code in sunxi_power_down

The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().

The two error messages say essentially the same thing anyway.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a

show more ...

Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
th

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6

show more ...

Merge pull request #1826 from smaeul/allwinner

allwinner: A few minor improvements

allwinner: Clean up CPU ops functions

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-

allwinner: Clean up CPU ops functions

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-off-by: Samuel Holland <samuel@sholland.org>

show more ...

Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2

Allwinner/pmic v2

allwinner: Prepare for executing code on the management processor

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM c

allwinner: Prepare for executing code on the management processor

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

allwinner: Pass FDT address to sunxi_pmic_setup()

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use

allwinner: Pass FDT address to sunxi_pmic_setup()

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use the
information contained therein to setup some initial power rails.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

allwinner: H6: Factor out I2C platform setup

In the H6 platform code there is a routine to do the platform
initialisation of the R_I2C controller. We will need a very similar
setup routine to initia

allwinner: H6: Factor out I2C platform setup

In the H6 platform code there is a routine to do the platform
initialisation of the R_I2C controller. We will need a very similar
setup routine to initialise the RSB controller on the A64.

Move this code to sunxi_common.c and generalise it to support all SoCs
and also to cover the related RSB bus.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

allwinner: Introduce GPIO helper function

Many boards without a dedicated PMIC contain simple regulators, which
can be controlled via GPIO pins.

To later allow turning them off easily, introduce a

allwinner: Introduce GPIO helper function

Many boards without a dedicated PMIC contain simple regulators, which
can be controlled via GPIO pins.

To later allow turning them off easily, introduce a simple function to
configure a given pin as a GPIO out pin and set it to the desired level.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

allwinner: Export sunxi_private.h

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will

allwinner: Export sunxi_private.h

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...