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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3128.heb4fc8a10985fdeaa0010e60db8a713fb5a4c104 Mon Oct 16 06:49:44 UTC 2017 David Wu <david.wu@rock-chips.com> clk: rockchip: Add rk3128 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I973b5f50b81559f054ca552ab69ec176cbe3abaa
Signed-off-by: David Wu <david.wu@rock-chips.com>
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3128.ceb4fc8a10985fdeaa0010e60db8a713fb5a4c104 Mon Oct 16 06:49:44 UTC 2017 David Wu <david.wu@rock-chips.com> clk: rockchip: Add rk3128 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I973b5f50b81559f054ca552ab69ec176cbe3abaa
Signed-off-by: David Wu <david.wu@rock-chips.com>