Searched hist:e7ca4433fa591233e7e2912b689ab56e531f9775 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_x2.h | e7ca4433fa591233e7e2912b689ab56e531f9775 Thu Jan 20 06:01:04 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x2.S | e7ca4433fa591233e7e2912b689ab56e531f9775 Thu Jan 20 06:01:04 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | e7ca4433fa591233e7e2912b689ab56e531f9775 Thu Jan 20 06:01:04 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | e7ca4433fa591233e7e2912b689ab56e531f9775 Thu Jan 20 06:01:04 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
|