1 /* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X2_H 8 #define CORTEX_X2_H 9 10 #define CORTEX_X2_MIDR U(0x410FD480) 11 12 /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X2_BHB_LOOP_COUNT U(32) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20 #define CORTEX_X2_CPUECTLR_EL1_WS_THR_DISABLE_ALL_BITS (ULL(0xFF) << 18) 21 22 /******************************************************************************* 23 * CPU Auxiliary Control register 3 specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2 26 27 /******************************************************************************* 28 * CPU Power Control register specific definitions 29 ******************************************************************************/ 30 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 31 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 32 33 /******************************************************************************* 34 * CPU Auxiliary Control Register definitions 35 ******************************************************************************/ 36 #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 37 #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 38 39 /******************************************************************************* 40 * CPU Auxiliary Control Register 2 definitions 41 ******************************************************************************/ 42 #define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 43 #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 44 45 /******************************************************************************* 46 * CPU Auxiliary Control Register 4 definitions 47 ******************************************************************************/ 48 #define CORTEX_X2_CPUACTLR4_EL1 S3_0_C15_C1_3 49 50 /******************************************************************************* 51 * CPU Auxiliary Control Register 5 definitions 52 ******************************************************************************/ 53 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 54 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 55 56 /******************************************************************************* 57 * CPU Implementation Specific Selected Instruction registers 58 ******************************************************************************/ 59 #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 60 #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 61 #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 62 #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 63 64 #ifndef __ASSEMBLER__ 65 long check_erratum_cortex_x2_3701772(long cpu_rev); 66 #endif /* __ASSEMBLER__ */ 67 68 #endif /* CORTEX_X2_H */ 69