1c6ac4df6Sjohpow01 /* 2ae6c7c97SGovindraj Raja * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3c6ac4df6Sjohpow01 * 4c6ac4df6Sjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5c6ac4df6Sjohpow01 */ 6c6ac4df6Sjohpow01 7c6ac4df6Sjohpow01 #ifndef CORTEX_X2_H 8c6ac4df6Sjohpow01 #define CORTEX_X2_H 9c6ac4df6Sjohpow01 10c6ac4df6Sjohpow01 #define CORTEX_X2_MIDR U(0x410FD480) 11c6ac4df6Sjohpow01 121fe4a9d1SBipin Ravi /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ 131fe4a9d1SBipin Ravi #define CORTEX_X2_BHB_LOOP_COUNT U(32) 141fe4a9d1SBipin Ravi 15c6ac4df6Sjohpow01 /******************************************************************************* 16c6ac4df6Sjohpow01 * CPU Extended Control register specific definitions 17c6ac4df6Sjohpow01 ******************************************************************************/ 18c6ac4df6Sjohpow01 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 19e7ca4433SBipin Ravi #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20*2c0467afSJohn Powell #define CORTEX_X2_CPUECTLR_EL1_WS_THR_DISABLE_ALL_BITS (ULL(0xFF) << 18) 21c6ac4df6Sjohpow01 22c6ac4df6Sjohpow01 /******************************************************************************* 23b01a93d7SSona Mathew * CPU Auxiliary Control register 3 specific definitions. 24b01a93d7SSona Mathew ******************************************************************************/ 25b01a93d7SSona Mathew #define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2 26b01a93d7SSona Mathew 27b01a93d7SSona Mathew /******************************************************************************* 28c6ac4df6Sjohpow01 * CPU Power Control register specific definitions 29c6ac4df6Sjohpow01 ******************************************************************************/ 30c6ac4df6Sjohpow01 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 31c6ac4df6Sjohpow01 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 32c6ac4df6Sjohpow01 331db6cd60Sjohpow01 /******************************************************************************* 3463446c27SBipin Ravi * CPU Auxiliary Control Register definitions 3563446c27SBipin Ravi ******************************************************************************/ 3663446c27SBipin Ravi #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 3763446c27SBipin Ravi #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 3863446c27SBipin Ravi 3963446c27SBipin Ravi /******************************************************************************* 40bc0f84deSBipin Ravi * CPU Auxiliary Control Register 2 definitions 41bc0f84deSBipin Ravi ******************************************************************************/ 42bc0f84deSBipin Ravi #define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 43bc0f84deSBipin Ravi #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 44bc0f84deSBipin Ravi 45bc0f84deSBipin Ravi /******************************************************************************* 46ce64ea6eSJohn Powell * CPU Auxiliary Control Register 4 definitions 47ce64ea6eSJohn Powell ******************************************************************************/ 48ce64ea6eSJohn Powell #define CORTEX_X2_CPUACTLR4_EL1 S3_0_C15_C1_3 49ce64ea6eSJohn Powell 50ce64ea6eSJohn Powell /******************************************************************************* 511db6cd60Sjohpow01 * CPU Auxiliary Control Register 5 definitions 521db6cd60Sjohpow01 ******************************************************************************/ 531db6cd60Sjohpow01 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 544dff7594SBipin Ravi #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 551db6cd60Sjohpow01 56c060b533SBipin Ravi /******************************************************************************* 57c060b533SBipin Ravi * CPU Implementation Specific Selected Instruction registers 58c060b533SBipin Ravi ******************************************************************************/ 59c060b533SBipin Ravi #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 60c060b533SBipin Ravi #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 61c060b533SBipin Ravi #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 62c060b533SBipin Ravi #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 63c060b533SBipin Ravi 64ae6c7c97SGovindraj Raja #ifndef __ASSEMBLER__ 65ae6c7c97SGovindraj Raja long check_erratum_cortex_x2_3701772(long cpu_rev); 66ae6c7c97SGovindraj Raja #endif /* __ASSEMBLER__ */ 67ae6c7c97SGovindraj Raja 68c6ac4df6Sjohpow01 #endif /* CORTEX_X2_H */ 69