Searched hist:e3d1bbdb08f643ad54e79c678d9f8cadaf63d4ce (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/aspeed/ast2700/include/ |
| H A D | platform_reg.h | e3d1bbdb08f643ad54e79c678d9f8cadaf63d4ce Tue Jun 18 09:02:49 UTC 2024 Kevin Chen <kevin_chen@aspeedtech.com> feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| H A D | platform_def.h | e3d1bbdb08f643ad54e79c678d9f8cadaf63d4ce Tue Jun 18 09:02:49 UTC 2024 Kevin Chen <kevin_chen@aspeedtech.com> feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| /rk3399_ARM-atf/plat/aspeed/ast2700/ |
| H A D | plat_helpers.S | e3d1bbdb08f643ad54e79c678d9f8cadaf63d4ce Tue Jun 18 09:02:49 UTC 2024 Kevin Chen <kevin_chen@aspeedtech.com> feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| H A D | plat_bl31_setup.c | e3d1bbdb08f643ad54e79c678d9f8cadaf63d4ce Tue Jun 18 09:02:49 UTC 2024 Kevin Chen <kevin_chen@aspeedtech.com> feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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