185f199b7SChia-Wei Wang/* 285f199b7SChia-Wei Wang * Copyright (c) 2023, Aspeed Technology Inc. 385f199b7SChia-Wei Wang * 485f199b7SChia-Wei Wang * SPDX-License-Identifier: BSD-3-Clause 585f199b7SChia-Wei Wang */ 685f199b7SChia-Wei Wang 785f199b7SChia-Wei Wang#include <asm_macros.S> 885f199b7SChia-Wei Wang#include <assert_macros.S> 985f199b7SChia-Wei Wang#include <arch.h> 1085f199b7SChia-Wei Wang#include <cortex_a35.h> 1185f199b7SChia-Wei Wang#include <platform_def.h> 1285f199b7SChia-Wei Wang 13*564e073cSChia-Wei Wang .globl platform_mem_init 1485f199b7SChia-Wei Wang .globl plat_is_my_cpu_primary 1585f199b7SChia-Wei Wang .globl plat_my_core_pos 1685f199b7SChia-Wei Wang .globl plat_secondary_cold_boot_setup 1785f199b7SChia-Wei Wang .globl plat_get_syscnt_freq2 1885f199b7SChia-Wei Wang .globl plat_crash_console_init 1985f199b7SChia-Wei Wang .globl plat_crash_console_putc 2085f199b7SChia-Wei Wang .globl plat_crash_console_flush 2185f199b7SChia-Wei Wang 22*564e073cSChia-Wei Wang/* void platform_mem_init(void); */ 23*564e073cSChia-Wei Wangfunc platform_mem_init 24*564e073cSChia-Wei Wang /* DRAM init. is done by preceding MCU */ 25*564e073cSChia-Wei Wang ret 26*564e073cSChia-Wei Wangendfunc platform_mem_init 27*564e073cSChia-Wei Wang 2885f199b7SChia-Wei Wang/* unsigned int plat_is_my_cpu_primary(void); */ 2985f199b7SChia-Wei Wangfunc plat_is_my_cpu_primary 3085f199b7SChia-Wei Wang mrs x0, mpidr_el1 3185f199b7SChia-Wei Wang and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 3285f199b7SChia-Wei Wang cmp x0, #PLATFORM_CORE_PRIMARY 3385f199b7SChia-Wei Wang cset w0, eq 3485f199b7SChia-Wei Wang ret 3585f199b7SChia-Wei Wangendfunc plat_is_my_cpu_primary 3685f199b7SChia-Wei Wang 3785f199b7SChia-Wei Wang/* unsigned int plat_my_core_pos(void); */ 3885f199b7SChia-Wei Wangfunc plat_my_core_pos 3985f199b7SChia-Wei Wang mrs x0, mpidr_el1 4085f199b7SChia-Wei Wang mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER 4185f199b7SChia-Wei Wang and x1, x0, #MPIDR_CPU_MASK 4285f199b7SChia-Wei Wang and x0, x0, #MPIDR_CLUSTER_MASK 4385f199b7SChia-Wei Wang madd x0, x0, x2, x1 4485f199b7SChia-Wei Wang ret 4585f199b7SChia-Wei Wangendfunc plat_my_core_pos 4685f199b7SChia-Wei Wang 47*564e073cSChia-Wei Wang/* void plat_secondary_cold_boot_setup (void); */ 48*564e073cSChia-Wei Wangfunc plat_secondary_cold_boot_setup 49*564e073cSChia-Wei Wang mov x0, xzr 50*564e073cSChia-Wei Wang bl plat_my_core_pos 51*564e073cSChia-Wei Wang mov_imm x1, SCU_CPU_SMP_EP0 52*564e073cSChia-Wei Wang add x1, x1, x0, lsl #3 53*564e073cSChia-Wei Wang 54*564e073cSChia-Wei Wangpoll_smp_mbox_go: 55*564e073cSChia-Wei Wang wfe 56*564e073cSChia-Wei Wang ldr x0, [x1] 57*564e073cSChia-Wei Wang cmp x0, xzr 58*564e073cSChia-Wei Wang beq poll_smp_mbox_go 59*564e073cSChia-Wei Wang br x0 60*564e073cSChia-Wei Wangendfunc plat_secondary_cold_boot_setup 61*564e073cSChia-Wei Wang 6285f199b7SChia-Wei Wang/* int plat_crash_console_init(void); */ 6385f199b7SChia-Wei Wangfunc plat_crash_console_init 6485f199b7SChia-Wei Wang mov_imm x0, CONSOLE_UART_BASE 6585f199b7SChia-Wei Wang mov_imm x1, CONSOLE_UART_CLKIN_HZ 6685f199b7SChia-Wei Wang mov_imm x2, CONSOLE_UART_BAUDRATE 6785f199b7SChia-Wei Wang b console_16550_core_init 6885f199b7SChia-Wei Wangendfunc plat_crash_console_init 6985f199b7SChia-Wei Wang 7085f199b7SChia-Wei Wang/* int plat_crash_console_putc(int); */ 7185f199b7SChia-Wei Wangfunc plat_crash_console_putc 7285f199b7SChia-Wei Wang mov_imm x1, CONSOLE_UART_BASE 7385f199b7SChia-Wei Wang b console_16550_core_putc 7485f199b7SChia-Wei Wangendfunc plat_crash_console_putc 7585f199b7SChia-Wei Wang 7685f199b7SChia-Wei Wang/* void plat_crash_console_flush(void); */ 7785f199b7SChia-Wei Wangfunc plat_crash_console_flush 7885f199b7SChia-Wei Wang mov_imm x0, CONSOLE_UART_BASE 7985f199b7SChia-Wei Wang b console_16550_core_flush 8085f199b7SChia-Wei Wangendfunc plat_crash_console_flush 81