Searched hist:dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | sys_proto.h | dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 Sat Jul 18 00:07:52 UTC 2015 Vladimir Zapolskiy <vz@mleia.com> nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
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| H A D | clk.h | dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 Sat Jul 18 00:07:52 UTC 2015 Vladimir Zapolskiy <vz@mleia.com> nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | devices.c | dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 Sat Jul 18 00:07:52 UTC 2015 Vladimir Zapolskiy <vz@mleia.com> nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
|
| /rk3399_rockchip-uboot/drivers/mtd/nand/ |
| H A D | Makefile | dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 Sat Jul 18 00:07:52 UTC 2015 Vladimir Zapolskiy <vz@mleia.com> nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
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